Analog (Integrated) Circuit Design
VDD, VCC, VSS, VEE or GND, plus a suitable suffix. Examples: VDD1, VDD_AMP, vdd_ldo_out, VSS_ANA (uppercase means connected to a pin, lowercase means a VDD is created on-chip by, e.g., an LDO).VDD/VSS for CMOS and VCC/GND for bipolar circuits. In BiCMOS circuits VDD/VSS are preferred, as usually, the digital content is the major part.di_ (for digital input) or do_ (for digital output). Example: di_ctrl1. In the rare case of a bi-directional digital signal dio_ can be used.di_pon is active-high, di_pon_b is active-low (_b standing for the negating “bar”); as an alternative, this last signal could be named di_disable. di_reset is an active-high reset, but often a reset is active-low, so it needs to be named di_reset_b (an alternative is di_resetn).do_comp_1v2 or di_poweron_3v3.do_adc[7:0].v for a voltage signal or i for a current signal. It is often useful to include a value for bias signals or make the naming meaningful. RF signals, which are often neither voltage nor current signals, start the name with rf_. Examples: Signal and pin names like ibias_30u (30uA of bias current), vbg_1v2 (a bandgap voltage of 1.2V), vin_p, v_filt_out_n, and rf_lna_i speak for themselves._i and _o might be useful if a clear direction is obvious in the signal flow. If a signal is bi-directional, it is better to skip _io. If using _p or _n in combination with _i or _o then use _pi/_ni or _po/_no.input, output, or inout to indicate signal flow. Power supply pins are of inout type.SVN is often preferable to GIT for binary data.Rstab or simply use R1, R2, etc.). Use iterated instances to clean up the circuit. Use wire bundles to clean up circuits where useful. A clever technique is to use bundles and iterated instances to efficiently draw large resistor ladders, for example (however, use with care).vdd, vss, pon, pon_b) are often better done with connection-by-name instead of drawing a wire.net0032 are of not much help).I1 or I2; better is amp1, inv2, etc. (a descriptor in a tool output like I1/I13/I5/net017 is not helpful; compare that to adc1/bias/bg/vref_int).GIGAPROJECT, the cells which are changed in the second design step are prefixed with g2_, like g2_amp_bias. Of course, more letters as a project abbreviation are useful if a name collision is likely to happen._ to break words instead of CamelCase, like amp_bias_startup.vref_int when connecting two leaf cells with the pin names vref_int_o and vref_int_i.L and decoupling C) and slow transients of bias nodes after disturbance.vdd/vss from each other!vdd and vss lines close to each other (incl. bond wires and PCB traces)! This minimizes L and coupling factor k.vdd or vss, or another node, depending on the circuit)!iverilog -g2005 -tnull FILE.v) or Verilator (verilator --lint-only -Wall FILE.v)._i) and outputs (ending with _o). IO signals are using _io. Active-low signals have an n or b in their name (coming before the direction), like reset_ni. Use comments to explain the intention._w (for Verilog wire) or _r (for Verilog reg) to make their function clear. This is not required in SystemVerilog where the unified type logic should be used.assign statement for logic as this often is easier to read than an always @(*) block. The ternary operator COND ? TRUE : FALSE can help with conditional assignments and is often a better choice than a (nested) if ... else statement.reg or wire.localparam in a module to make the code easier to follow. Name parameters in UPPERCASE.`default_nettype none at the beginning of a file containing a module definition. After the module you can use `default_nettype wire. This will add a safety net against typos in signal names.always @(*) begin ... end instead of spelling out the signals in the sensitivity list. Forgetting a signal could lead to serious mismatches between simulation and HW.localparam or module parameter.=) in always @(*) blocks, and only non-blocking assignments (<=) in clocked always @(posedge ...) blocks.set (for setting, i.e., Q=1) and res (for resetting, i.e., Q=0). Asynchronous set and reset should be called pre (for presetting) and clr (for clearing). In this way it is immediately clear whether a control input is acting independent of the clk (i.e., asynchronous) or dependent on the clk (i.e., synchronous).