Improved Current Mirrors

Analog (Integrated) Circuit Design

10 Improved Current Mirrors

Improved Current Mirrors

Figure 47: A cascoded current mirror using a biasing voltage to set the cascode gate potential.

In Section 6, we looked into the operation of the basic current mirror. While it is a useful structure and easy to implement, its output resistance is limited by the MOSFET’s output conductance to \(r_\mathrm{out} = g_\mathrm{ds}^{-1}\), and its current mirroring accuracy is also limited by channel-length modulation effects since the \(V_\mathrm{DS}\) of the output transistor varies with load conditions, and is thus different from the \(V_\mathrm{DS}\) of the reference transistor.

Using the cascode principle introduced in Section 9, we can improve both the output resistance and the current mirroring accuracy of the current mirror by adding a cascode stage (shown in blue). The improved current mirror structure is shown in Figure 47.

Improved Current Mirrors

1. Increased output resistance, as we have seen in Equation 34.
2. Improved current mirroring accuracy, since the cascode transistors help to keep the drain-source voltage of the output transistor nearly constant and equal to that of the reference transistor.

We can see that by introducing the cascode transistors we achieve the following benefits:

There are several ways to implement the bias voltage \(V_\mathrm{bias}\) for setting the cascode transistors’ gate potential. One simple option is to use a biasing resistor \(R_\mathrm{bias}\) (highlighted in blue) as shown in Figure 48, which is called a “high-swing” cascode structure.

Improved Current Mirrors

Figure 48: A high-swing cascoded current mirror.

A high-swing cascoded current mirror. The voltage drop across the resistor \(R_\mathrm{bias}\) sets the drain-source voltage of the lower transistors (together with the sizing of the MOSFETs).

Improved Current Mirrors

\[ r_\mathrm{out} = r_\mathrm{ds,casc} + r_\mathrm{ds} \cdot (1 + g_\mathrm{m,casc} \cdot r_\mathrm{ds,casc}). \tag{37}\]

The output impedance according to Equation 35 of the improved current mirror is approximately given by (\(r_\mathrm{ds,casc} = g_\mathrm{ds,casc}^{-1}\) and \(g_\mathrm{m,casc}\) are the parameters of the cascode transistor, and \(r_\mathrm{ds} = g_\mathrm{ds}^{-1}\) is the parameter of the bottom transistor):

We can bias the gate voltages of the cascode transistors with any suitable bias circuit, but a simple way is to use a resistor \(R_\mathrm{bias}\) as shown in the figure. The voltage drop across this resistor sets the drain-source voltage of the lower transistors (together with the sizing of the MOSFETs). By choosing a sufficiently large value for \(R_\mathrm{bias}\), we can ensure that both transistors remain in saturation for the desired range of output currents. The cascode transistors make sure that the drain-source voltage of the output transistor remains nearly constant and equal to the drain-source voltage of the reference transistor, thus improving the current mirroring accuracy.

Another option for an improved current mirror is to use source degeneration with a resistor. This configuration is shown in Figure 49. Here, the source degeneration resistors \(R_\mathrm{deg}\) help to stabilize the operating point of the current mirror using series feedback.

Improved Current Mirrors

Figure 49: A current mirror with resistive degeneration.

Improved Current Mirrors

\[ r_\mathrm{out} = r_\mathrm{ds} + R_\mathrm{deg} \cdot (1 + g_\mathrm{m}\cdot r_\mathrm{ds}). \tag{38}\]

Here, similar to Equation 37, the output resistance can be approximated by

A third popular option to implement an improved current mirror is to use the so-called regulated current mirror, which uses an additional amplifier to sense the drain potential of the bottom transistor and keep it constant (Hosticka 1979). Note that the output current will not change if the \(V_\mathrm{DS}\) of the bottom transistor is kept constant. We can use any suitable amplifier for this purpose, e.g., a simple OTA as introduced in Section 8. In the most basic form, we use a common-source stage with a current mirror load as shown in blue in Figure 50.

Improved Current Mirrors

Figure 50: A regulated-cascode current mirror.

A regulated-cascode current mirror. The simple common-source amplifier is used to keep the drain voltage of the bottom transistor constant, thus improving the current mirroring accuracy and output resistance.

Improved Current Mirrors

\[ \begin{split} r_\mathrm{out} &= r_\mathrm{ds,casc} + r_\mathrm{ds} \cdot [1 + g_\mathrm{m,casc} \cdot r_\mathrm{ds,casc} \cdot (1 + g_\mathrm{maux} / g_\mathrm{dsaux})] \\ & \approx r_\mathrm{ds} \cdot g_\mathrm{m,casc} \cdot r_\mathrm{ds,casc} \cdot g_\mathrm{m,aux} \cdot r_\mathrm{ds,aux} \end{split} \tag{39}\]

We assume the voltage gain of the auxiliary amplifier to be \(A_\mathrm{v} = g_\mathrm{maux} / g_\mathrm{dsaux}\), where \(g_\mathrm{maux}\) and \(g_\mathrm{dsaux}\) are the transconductance and output conductance of the auxiliary amplifier, respectively. The output resistance of the regulated cascode current mirror can then be approximated by

which, compared to Equation 37, is further improved by the gain of the auxiliary amplifier.

We now want to size all these current mirror structures and simulate their performance. We try to size them for similar chip area in order to get a fair comparison. We assume a reference current of \(I_\mathrm{bias} = 50\,\mu\text{A}\) and a mirror ratio of 1:1. We size for a minimum voltage headroom for the current sources of \(V_\mathrm{DS,min} = 0.4\,\text{V}\). The calculations are summarized in this sizing notebook.

One structure cannot honor that number, and it is worth seeing why before we look at the simulation results. In the regulated cascode the auxiliary amplifier holds the drain of the bottom device at its own gate-source voltage, so \(V_\mathrm{DS1} = V_\mathrm{GSaux} \approx 0.37\,\text{V}\), and the cascode transistor stacked on top still needs its own \(V_\mathrm{ds,sat} \approx 0.2\,\text{V}\). Its compliance voltage is therefore about \(0.57\,\text{V}\), not \(0.4\,\text{V}\) — forcing it to \(0.4\,\text{V}\) would simply leave the cascode device in triode, where it does no cascoding at all. This is the drawback we will address in Section 10.1, and it is clearly visible in the simulated output resistance below.

The resulting circuits are drawn in Figure 51. The testbench simulates the dc output characteristics of all four current mirror variations (the three improved ones and the basic one for reference). The testbench also runs a Monte-Carlo simulation to evaluate the current mirroring accuracy under device mismatch (see Section 8.6.1).

Improved Current Mirrors

Figure 51: Simulation schematic of the improved current mirrors.

Improved Current Mirrors

Table 3: Simulated small-signal output resistance versus output voltage

Structure	\(r_\mathrm{out}\) at \(V_\mathrm{out} = 0.5\,\text{V}\)	at \(1.0\,\text{V}\)	at \(1.5\,\text{V}\)
Basic current mirror	\(150\,\text{k}\Omega\)	\(260\,\text{k}\Omega\)	\(360\,\text{k}\Omega\)
High-swing cascode	\(720\,\text{k}\Omega\)	\(1.5\,\text{M}\Omega\)	\(2.4\,\text{M}\Omega\)
Source degeneration	\(200\,\text{k}\Omega\)	\(350\,\text{k}\Omega\)	\(490\,\text{k}\Omega\)
Regulated cascode	\(710\,\text{k}\Omega\)	\(2.8\,\text{M}\Omega\)	\(3.7\,\text{M}\Omega\)

The output characteristics from the dc sweep simulation are shown in Figure 52, and a zoom-in in Figure 53. Since the output resistance is nothing but the reciprocal slope of these curves, \(r_\mathrm{out} = \mathrm{d}V_\mathrm{out}/\mathrm{d}I_\mathrm{out}\), the lower panel of Figure 53 plots it directly: a flat output characteristic and a high output resistance are two views of the same data.

The first thing to take away from that panel is that \(r_\mathrm{out}\) is not a single number: it collapses steeply below the compliance voltage, where the output devices enter triode, and it keeps growing with \(V_\mathrm{out}\) throughout the useful range. Any value we quote is therefore only meaningful together with the bias point at which it was taken:

The ordering is what the theory predicts: the two cascoded structures gain roughly an order of magnitude over the basic mirror, and the regulated cascode ends up highest, as Equation 39 suggests. Note, though, that the regulated cascode only pulls ahead of the high-swing cascode once its auxiliary amplifier has enough headroom to gain; at \(0.5\,\text{V}\) the two are still on par. The source-degenerated mirror, in contrast, improves the output resistance only mildly (by about a factor of \(1.4\)), since the degeneration factor \(1 + g_\mathrm{m}R_\mathrm{deg}\) of Equation 38 stays modest for a practical voltage drop across \(R_\mathrm{deg}\). Its strength lies elsewhere, as we will see next.

Improved Current Mirrors

Figure 52: Output characteristics of the four current mirror structures.

Improved Current Mirrors

Figure 53: Output characteristics of the four current mirror structures (zoom in, upper panel) and the resulting small-signal output resistance \(r_\mathrm{out} = \mathrm{d}V_\mathrm{out}/\mathrm{d}I_\mathrm{out}\) obtained as the reciprocal slope of these curves (lower panel, logarithmic).

Output characteristics of the four current mirror structures (zoom in, upper panel) and the resulting small-signal output resistance \(r_\mathrm{out} = \mathrm{d}V_\mathrm{out}/\mathrm{d}I_\mathrm{out}\) obtained as the reciprocal slope of these curves (lower panel, logarithmic). The high-swing cascode and the regulated cascode achieve significantly higher output resistance compared to the basic and degenerated current mirror. Note the steep collapse of \(r_\mathrm{out}\) below the compliance voltage, where the output transistors leave saturation, and that \(r_\mathrm{out}\) keeps rising with \(V_\mathrm{out}\) well inside the useful range.

Improved Current Mirrors

Figure 54: Monte Carlo analysis of the four current mirror structures showing current distribution and fitted Gaussian curves.

We now look into the results of the Monte-Carlo simulation to evaluate the current mirroring accuracy under device mismatch using 500 runs and a compliance voltage of 0.4 V. The results are summarized in Figure 54. We can see that the high-swing cascode and the regulated cascode achieve a very precise nominal current accuracy of almost 50 µA. However, the source-degenerated current mirror shows a significantly reduced spread of the output current, indicating a reduced mismatch of the poly-silicon resistors compared to the MOSFETs.

It is instructive to also look at the reverse side of the coin. The relative spread comes out as \(0.42\,\%\) for the basic mirror, \(0.24\,\%\) for the source-degenerated one, but \(0.83\,\%\) for the high-swing cascode and \(1.79\,\%\) for the regulated cascode. The two cascoded structures thus match worse than the plain current mirror, because the cascode devices (and, in the regulated case, the auxiliary amplifier with its own bias current sources) contribute their own mismatch on top of that of the bottom transistor pair. Output resistance and current accuracy are therefore not improved by the same measure: a cascode buys you the former and can cost you the latter. This is a good example of why a structure should never be selected on a single figure of merit.

Improved Current Mirrors

Figure 55: Output noise current vs. frequency for the four current mirror structures.

Finally, we compare the output noise of the four different current mirror structures in Figure 55. We can see that the regulated cascode has the highest output noise due to the additional auxiliary amplifier, while the source-degenerated mirror has the lowest output noise.

10.1 Low-Voltage Regulated Current Mirror

Low-Voltage Regulated Current Mirror

Figure 56: A low-voltage regulated-cascode current mirror.

The one drawback of the regulated cascode current mirror shown in Figure 50 is its relatively high compliance voltage, which is due to the fact that \(V_\mathrm{DS1} = V_\mathrm{GSaux}\). One alternative implementation that reduces the compliance voltage is shown in Figure 56. Here, we use a differential common-gate stage (essentially a current mirror with inputs at the sources of the transistors) as an auxiliary amplifier, which significantly reduces the required voltage headroom, at the expense of a slightly increased circuit complexity (Ivanov and Filanovsky 2004). However, the bias current sources \(I_\mathrm{bias2,3}\) of the auxiliary amplifier introduce some additional noise and mismatch.

A low-voltage regulated-cascode current mirror. The differential common-gate error amplifier is used to keep the drain voltage of the bottom transistors constant, thus improving the current mirroring accuracy and output resistance.

10.2 Current Source Variations Summary

Current Source Variations Summary

• For general applications where output resistance and current accuracy are not critical, the basic current mirror can be used. It also has the lowest compliance voltage since only one transistor is stacked.
• The high-swing cascode current mirror is a good choice when higher output resistance is needed, while still keeping the circuit relatively simple. Be aware that the added cascode devices roughly double the current spread under mismatch compared to the basic mirror.

In summary, we can classify the usage of the different current mirror structures as follows:

Current Source Variations Summary

• The source-degenerated current mirror is a good choice when the best current matching and low output noise are required. The additional voltage headroom that is dropped across the source degeneration can be adapted (higher is better), but a minimum value of 0.1 V should be used. Note that its output resistance is only mildly improved.

Current Source Variations Summary

• The regulated cascode current mirror is the best choice when the highest output resistance is required, and the additional complexity, output noise, and a roughly four-fold larger current spread under mismatch are acceptable.
• The low-voltage regulated cascode current mirror is a good alternative to the regulated cascode when a low compliance voltage is required.

Please note that the absolute performance can be tweaked by proper sizing. The examples shown here are sized for similar chip area and a fair comparison.

10.3 Current Mirror Matching

Current Mirror Matching

Figure 57: A current mirror pair with resistive degeneration.

Looking at the different current mirror architectures in Section 10, we can see that the current mirror matching is dominated by the bottom transistor pair (assuming equal \(V_\mathrm{DS}\)), with the exception of the resistively degenerated current mirror. We asserted that the matching of the resistively-degenerated current mirror is improved due to the lower impact of MOSFET mismatch compared to resistor mismatch. We will now substantiate this claim.

We will derive the current mirror matching of a pair of resistively-degenerated current mirror transistors shown in Figure 49.

Current Mirror Matching

\[ \begin{split} \sigma^2\left\{\frac{\Delta I_\mathrm{D}}{I_\mathrm{D}}\right\} & = \frac{\sigma^2\left\{\Delta V_\mathrm{th}\right\}}{(V_\mathrm{drv} + V_\mathrm{deg})^2} + \left( \frac{V_\mathrm{drv}}{V_\mathrm{drv} + V_\mathrm{deg}} \right)^2 \cdot \sigma^2\left\{\frac{\Delta K}{K}\right\} \\ & + \left( \frac{V_\mathrm{deg}}{V_\mathrm{drv} + V_\mathrm{deg}} \right)^2 \cdot \sigma^2\left\{\frac{\Delta R}{R}\right\}. \end{split} \tag{40}\]

The variance \(\sigma^2\) of the output current difference, normalized to the current, is given by (Gray et al. 2009)

The definition of \(V_\mathrm{drv}\) is adapted here and understood as half of the \(V_\mathrm{DS}\) saturation voltage, i.e., \(V_\mathrm{drv} = V_\mathrm{DS,sat} / 2 \approx I_\mathrm{D}/ g_\mathrm{m}\). The degeneration voltage is the voltage drop across the degeneration resistors and given by \(V_\mathrm{deg} = I_\mathrm{D}\cdot R\).

The standard deviation of the resistor \(\sigma\left\{\Delta R / R\right\}\) can be calculated using Equation 32. Further, the threshold voltage mismatch \(\sigma\left\{\Delta V_\mathrm{th}\right\}\) can be calculated using Equation 28.

By using the approximation of Equation 4, we can express Equation 40 in terms of our preferred sizing parameter \(g_\mathrm{m}/ I_\mathrm{D}\):

Current Mirror Matching

\[ \begin{split} \sigma^2\left\{\frac{\Delta I_\mathrm{D}}{I_\mathrm{D}}\right\} & = \frac{\sigma^2\left\{\Delta V_\mathrm{th}\right\}}{[(g_\mathrm{m}/I_\mathrm{D})^{-1} + V_\mathrm{deg}]^2} + \left( \frac{1}{1 + V_\mathrm{deg}\cdot g_\mathrm{m}/I_\mathrm{D}} \right)^2 \cdot \sigma^2\left\{\frac{\Delta K}{K}\right\} \\ & + \left( \frac{V_\mathrm{deg} \cdot g_\mathrm{m}/I_\mathrm{D}}{1 + V_\mathrm{deg} \cdot g_\mathrm{m}/I_\mathrm{D}} \right)^2 \cdot \sigma^2\left\{\frac{\Delta R}{R}\right\}. \end{split} \tag{41}\]

The standard deviation of the transconductance parameter mismatch \(\sigma\left\{\Delta K / K\right\}\) can be calculated similarly as (which is an alternative form to Equation 29)

Current Mirror Matching

\[ \sigma^2\left\{\frac{\Delta K}{K}\right\} = \sigma^2\left\{\Delta W\right\} \cdot \frac{1}{W^2} + \sigma^2\left\{\Delta L\right\} \cdot \frac{1}{L^2} + A_\mu^2 \cdot \frac{1}{W L}, \tag{42}\]

where \(\sigma\left\{\Delta W\right\}\) and \(\sigma\left\{\Delta L\right\}\) are the process-dependent absolute mismatch parameters for the width \(W\) and length \(L\), respectively. The mobility mismatch follows Pelgrom’s law like the threshold voltage, so it is described by an area-scaled constant \(A_\mu = \sigma\left\{\Delta \mu / \mu\right\} \cdot \sqrt{W L}\), which is the quantity listed in Table 4.

The standard deviations of the components of the SG13G2 process are summarized in Table 4. For mismatch calculations we can assume them to be uncorrelated.

Current Mirror Matching

Table 4: IHP SG13G2 device mismatch

Component	Matching Parameter	Value
Resistor rsil	\(\sigma\left\{\Delta R / R\right\} \cdot \sqrt{WL}\)	1.2 % µm
Resistor rppd	\(\sigma\left\{\Delta R / R\right\} \cdot \sqrt{WL}\)	1.5 % µm
Resistor rhigh	\(\sigma\left\{\Delta R / R\right\} \cdot \sqrt{WL}\)	5 % µm
MIM cap_cmim	\(\sigma\left\{\Delta C / C\right\} \cdot \sqrt{WL}\)	1 % µm (estimated)
MOSFET sg13_lv_nmos	\(\sigma\left\{\Delta V_\mathrm{th}\right\} \cdot \sqrt{WL}\)	3.9 mV µm
MOSFET sg13_lv_nmos	\(\sigma\left\{\Delta W\right\}\)	4 nm
MOSFET sg13_lv_nmos	\(\sigma\left\{\Delta L\right\}\)	2 nm
MOSFET sg13_lv_nmos	\(\sigma\left\{\Delta \mu/\mu\right\} \cdot \sqrt{WL}\)	0.5 % µm
MOSFET sg13_lv_pmos	\(\sigma\left\{\Delta V_\mathrm{th}\right\} \cdot \sqrt{WL}\)	2.2 mV µm
MOSFET sg13_lv_pmos	\(\sigma\left\{\Delta W\right\}\)	4 nm
MOSFET sg13_lv_pmos	\(\sigma\left\{\Delta L\right\}\)	2 nm
MOSFET sg13_lv_pmos	\(\sigma\left\{\Delta \mu/\mu\right\} \cdot \sqrt{WL}\)	0.33 % µm

Inspecting Equation 40 we can see that by implementing a common-source transistor without source degeneration (i.e., \(V_\mathrm{deg} = 0\)), the current mirror matching is dominated by the threshold voltage mismatch and the transconductance parameter mismatch of the MOSFETs:

Current Mirror Matching

\[ \sigma^2\left\{\frac{\Delta I_\mathrm{D}}{I_\mathrm{D}}\right\} = \sigma^2\left\{\Delta V_\mathrm{th}\right\} \left( \frac{g_\mathrm{m}}{I_\mathrm{D}} \right)^2 + \sigma^2\left\{\frac{\Delta K}{K}\right\} \tag{43}\]

\[ \sigma^2\left\{\frac{\Delta I_\mathrm{D}}{I_\mathrm{D}}\right\} = \sigma^2\left\{\frac{\Delta R}{R}\right\} \tag{44}\]

The first term in Equation 43 can be minimized by choosing a low \(g_\mathrm{m}/ I_\mathrm{D}\) ratio, while the latter term is minimized by increasing the device area (i.e., increasing \(W\) and \(L\)).

Looking at the resistively-degenerated current mirror, and using a large degeneration voltage \(V_\mathrm{deg}\), we can simplify Equation 41 to

indicating that now the current matching of the degenerated current mirror is defined by the resistor matching only. Since resistors can be matched considerably better than MOSFETs, this can lead to a significant improvement in current mirror accuracy, but only if the resistor is given enough area, as the worked example below will show.

Current Mirror Matching

Current Mirror Matching Calculation

Let us now calculate the current mirror matching of the simple current mirror. Using Equation 43, and using the sizing values of \(g_\mathrm{m}/ I_\mathrm{D}= 5\,\text{V}^{-1}\), \(W = 10\,\mu\text{m}\), and \(L = 5\,\mu\text{m}\), we can calculate the standard deviation of the transconductance parameter mismatch using Equation 42 and Table 4: \[ \sigma\left\{\frac{\Delta K}{K}\right\} = \sqrt{ \left( \frac{4\,\text{nm}}{10\,\mu\text{m}} \right)^2 + \left( \frac{2\,\text{nm}}{5\,\mu\text{m}} \right)^2 + \left( \frac{0.5\,\%\mu\text{m}}{\sqrt{10\,\mu\text{m} \cdot 5\,\mu\text{m}}} \right)^2 } = 0.09\,\%. \]

The standard deviation of the threshold voltage mismatch can be calculated using Equation 28 and Table 4: \[ \sigma\left\{\Delta V_\mathrm{th}\right\} = \frac{3.9\,\text{mV}\mu\text{m}}{\sqrt{10\,\mu\text{m} \cdot 5\,\mu\text{m}}} = 0.55\,\text{mV}. \]

Current Mirror Matching

Current Mirror Matching Calculation

Bringing both results into Equation 43, we get \[ \sigma\left\{\frac{\Delta I_\mathrm{D}}{I_\mathrm{D}}\right\} = \sqrt{ (0.55\,\text{mV} \cdot 5\,\text{V}^{-1})^2 + (0.09\,\%)^2} \approx 0.29\,\%. \] Comparing with the simulation results in Figure 54 for the basic current mirror, we can see that this gives a reasonable estimate compared to the standard deviation of about \(0.21\,\mu\text{A}/48.9\,\mu\text{A} = 0.43\,\%\) obtained from the Monte-Carlo simulation. The remaining discrepancy is due to simplifications in the analytical model (e.g., the square-law approximation).

Current Mirror Matching

Current Mirror Matching Calculation

Let us now calculate the current mirror matching of the resistively-degenerated current mirror. We can use Equation 41 to analyze this configuration. We use the sizing values of \(g_\mathrm{m}/ I_\mathrm{D}= 10\,\text{V}^{-1}\), \(W = 20\,\mu\text{m}\), and \(L = 3\,\mu\text{m}\), for the MOSFET, and \(V_\mathrm{deg} = 0.2\,\text{V}\), and \(W = 3\,\mu\text{m}\) / \(L = 45\,\mu\text{m}\) for the used rppd resistor (which at \(R_\square = 260\,\Omega\) gives the required \(R_\mathrm{deg} \approx 3.9\,\text{k}\Omega\)).

The standard deviation of the transconductance parameter mismatch can be calculated as \[ \sigma\left\{\frac{\Delta K}{K}\right\} = \sqrt{ \left( \frac{4\,\text{nm}}{20\,\mu\text{m}} \right)^2 + \left( \frac{2\,\text{nm}}{3\,\mu\text{m}} \right)^2 + \left( \frac{0.5\,\%\mu\text{m}}{\sqrt{20\,\mu\text{m} \cdot 3\,\mu\text{m}}} \right)^2 } = 0.09\,\%. \]

The standard deviation of the threshold voltage mismatch can be calculated as \[ \sigma\left\{\Delta V_\mathrm{th}\right\} = \frac{3.9\,\text{mV}\mu\text{m}}{\sqrt{20\,\mu\text{m} \cdot 3\,\mu\text{m}}} = 0.50\,\text{mV}. \]

Current Mirror Matching

Current Mirror Matching Calculation

The standard deviation of the resistor mismatch can be calculated using Equation 32 and Table 4: \[ \sigma\left\{\frac{\Delta R}{R}\right\} = \frac{1.5\,\%\mu\text{m}}{\sqrt{3\,\mu\text{m} \cdot 45\,\mu\text{m}}} = 0.13\,\%. \]

Plugging these results into Equation 41, we get \[ \begin{split} \sigma^2\left\{\frac{\Delta I_\mathrm{D}}{I_\mathrm{D}}\right\} =& \underbrace{\left( \frac{0.50\,\text{mV}}{0.1\,\text{V} + 0.2\,\text{V}} \right)^2}_{(0.17\,\%)^2} + \underbrace{\left( \frac{1}{1 + 0.2\,\text{V} \cdot 10\,\text{V}^{-1}} \cdot 0.09\,\% \right)^2}_{(0.03\,\%)^2} \\ & + \underbrace{\left( \frac{0.2\,\text{V} \cdot 10\,\text{V}^{-1}}{1 + 0.2\,\text{V} \cdot 10\,\text{V}^{-1}} \cdot 0.13\,\%\right)^2}_{(0.09\,\%)^2} \\ =& (0.19\,\%)^2. \end{split} \]

Current Mirror Matching

Current Mirror Matching Calculation

The three terms are worth reading individually. The degeneration has done its job on the MOSFET: the dominant threshold-voltage term is down to \(0.17\,\%\) and the transconductance-parameter term to a negligible \(0.03\,\%\), while the resistor contributes only \(0.09\,\%\). The total of \(0.19\,\%\) is a clear improvement over the \(0.29\,\%\) of the basic current mirror, and it matches the Monte-Carlo result in Figure 54 of about \(0.12\,\mu\text{A}/48.8\,\mu\text{A} = 0.24\,\%\) reasonably well.

Current Mirror Matching

Current Mirror Matching Calculation

The essential lesson of source degeneration is that it does not remove mismatch, it trades MOSFET mismatch for resistor mismatch — so the trade only pays off if the resistor is given enough area.

Current Mirror Matching

Current Mirror Matching Calculation

That is exactly why \(R_\mathrm{deg}\) is laid out here as a long, comparatively wide device (\(3 \times 45\,\mu\text{m}^2\)) instead of the minimum-width strip that would deliver the same \(3.9\,\text{k}\Omega\): a \(W = 1\,\mu\text{m}\) / \(L = 15\,\mu\text{m}\) resistor has the same resistance but nine times less area, which would raise its mismatch contribution from \(0.09\,\%\) to \(0.26\,\%\) and push the total back to \(0.31\,\%\) — no better than the basic mirror. Resistor area, not resistor value, is what buys the matching here.

References

Gray, Paul R., Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer. 2009. Analysis and Design of Analog Integrated Circuits. Wiley.

Hosticka, B. J. 1979. “Improvement of the gain of MOS amplifiers.” IEEE Journal of Solid-State Circuits 14 (6): 1111–14. https://doi.org/10.1109/jssc.1979.1051324.

Ivanov, Vadim V., and Igor M. Filanovsky. 2004. Operational Amplifier Speed and Accuracy Improvement. Kluwer Academic Publishers.

References