A Basic 5-Transistor OTA

Analog (Integrated) Circuit Design

8 A Basic 5-Transistor OTA

A Basic 5-Transistor OTA

Figure 32: The 5-transistor OTA.

Armed with the insights of basic transistor operation (Section 2 and Section 3) and the working knowledge of the current mirror (Section 4 and Section 6) as well as the differential pair (Section 7), we can now start to design our first real circuit. A fundamental (simple) circuit that is often used for basic tasks is the 5-transistor operational transconductance amplifier (OTA). A circuit diagram of this 5T-OTA is shown in Figure 32.

A Basic 5-Transistor OTA

Refresh MOSFET Basic Circuits

While we repeat the basics of elementary MOSFET amplifier stages (like common-source stage, common-gate stage, and current mirror) in this course material, the following compendium (Murmann 2013) is recommended for review. It is freely available at https://github.com/bmurmann/Book-on-MOS-stages.

In addition, we can highly recommend these references (Gray et al. 2009; Razavi 2017) for further study.

OPA vs. OTA

	OPA	OTA
Input impedance	\(\infty\)	\(\infty\)
Output resistance	\(0\) (voltage output)	\(\infty\) (current output)
Ideal gain	\(A_\mathrm{v} \rightarrow \infty\)	\(G \rightarrow \infty\)

• With a capacitive (high-ohmic) load, an OTA acts as a high-gain voltage amplifier
• An OTA is simpler — the simplest circuit that does the job is usually best

The operation is as follows: \(M_{1,2}\) form a differential pair which is biased by the current source \(M_5\). \(M_{5,6}\) form a current mirror, thus the input bias current \(I_\mathrm{bias}\) sets the bias current in the OTA. The differential pair \(M_{1,2}\) is loaded by the current mirror \(M_{3,4}\) which mirrors the drain current of \(M_1\) to the right side. Here, the currents from \(M_4\) and \(M_2\) are summed, and together with the conductance effective at the output node, a voltage builds up.

8.1 Voltage Buffer with OTA

We note that \(M_{1,2}\) and \(M_{3,4}\) need to be symmetric, thus will have the same \(W\) and \(L\) dimensioning. \(M_{5,6}\) we scale accordingly to set the correct bias current in the OTA.

Voltage Buffer with OTA

Figure 33: A voltage buffer (based on OTA) driving a capacitive load.

In order to design an OTA we need an application, and from this we need to derive the circuit specifications. We want to use this OTA to realize a voltage buffer which lightly loads an input voltage source and can drive a large capacitive load. Such a configuration is often used to, e.g., buffer a reference voltage that is needed (and thus loaded) by another circuit. The block diagram of this configuration is shown in Figure 33.

Voltage Buffer with OTA

Table 2: Voltage buffer specification

Specification	Value	Unit
Supply voltage	\(1.45 < \underline{1.5} < 1.55\)	V
Temperature range (industrial)	\(-40 < \underline{27} < 125\)	degC
Load capacitance \(C_\mathrm{load}\)	\(50\)	fF
Input voltage range (for buffering 2/3 bandgap voltage)	\(0.7 < \underline{0.8} < 0.9\)	V
Signal bandwidth (3 dB)	\(>10\)	MHz
Output voltage error	\(<3\)	%
Total output noise (rms)	\(<1\)	mVrms
Supply current (as low as possible)	\(<10\)	µA
Stability	stable for rated \(C_\mathrm{load}\)
Turn-on time (settled to with 1%)	\(<10\)	µs
Externally provided bias current (nominal)	\(20\)	µA

If the voltage gain of the OTA in Figure 33 is high, then \(V_\mathrm{out} \approx V_\mathrm{in}\). We now want to design an OTA for this application, fitting the following specification values (see Table 2). These values are rather typical of what could be expected for such a buffer design.

8.2 Large-Signal Analysis of the OTA

Large-Signal Analysis of the OTA

Figure 34: The 5-transistor OTA with external connections and load capacitor.

The first step when receiving a design task is to look at the specifications and see whether they make sense. The detailed performance of the design will be the result of the circuit simulation, but before we step into sizing we need to do a few simple calculations to (a) do back-of-the-envelope gauging if the specification makes sense, and (b) use the derived analytical equations as guide for the sizing procedure.

In terms of large-signal operation, we will now check whether the input and output voltage range, as well as the settling time can be roughly met. Since we do not know yet the resulting \(V_\mathrm{GS}\) of the transistors, we use \(0.6\,\text{V}\) as an initial guess. If we run into issues with that guess, we know how to later steer the sizing procedure. The follower configuration showing the transistor-level details including estimated operating points is shown in Figure 34.

The 5-transistor OTA with external connections and load capacitor. Estimated dc operating points are shown in blue.

Large-Signal Analysis of the OTA

• When the input is at its maximum of \(0.9\,\text{V}\), we see that we need to keep \(M_1\) in saturation. We can calculate that \(V_\mathrm{DS1} = V_\mathrm{DD}- |V_\mathrm{GS3}| + V_\mathrm{GS1} - V_\mathrm{in} = 1.45 - 0.6 + 0.6 - 0.9 = 0.55\,\text{V}\), which leaves enough margin.
• When the input is at its minimum of \(0.7\,\text{V}\), we see that the \(V_\mathrm{DS5}\) of \(M_5\) is calculated as \(V_\mathrm{DS5} = V_\mathrm{in} - V_\mathrm{GS1} = 0.7 - 0.6 = 0.1\,\text{V}\), so this leaves little margin, but we can make \(V_\mathrm{GS1}\) smaller, so it should work out.
• For the output voltage, when the output voltage is on the high side, it leaves \(|V_\mathrm{DS4}| = V_\mathrm{DD}- V_\mathrm{out} = 1.45 - 0.9 = 0.55\,\text{V}\), which is enough margin.

In summary, we think that we can make an NMOS-input OTA like the one in Figure 32 (and in Figure 34) work for the required supply and input and output voltages. If this would not work out, we need to look for further options, like a PMOS-input OTA or an NMOS/PMOS-input OTA.

Another large-signal specification item that we can quickly check is the settling time. Under slewing conditions, the complete bias current in the OTA is steered toward the output (try to understand why this is the case), so when the output capacitor is fully discharged and we assume just a linear ramp due to constant-current charging of the output capacitor, the settling time is

Large-Signal Analysis of the OTA

\[ T_\mathrm{slew} \approx \frac{C_\mathrm{load} \cdot V_\mathrm{out,max}}{I_\mathrm{tail}} = \frac{50 \cdot 10^{-15} \cdot 0.9}{10 \cdot 10^{-6}} = 4.5\,\text{ns}. \]

The small-signal settling (assuming one pole at the bandwidth corner frequency) leads to an approximate settling time (1% error corresponds to \(\approx 5 \tau\)) of \[ T_\mathrm{settle} \approx \frac{5}{2 \pi f_\mathrm{c}} = \frac{5}{2 \pi \cdot 10 \times 10^{6}} = 0.08\,\mu\text{s}. \]

Note that we have optimistically inserted the total supply current budget of \(10\,\mu\text{A}\) for \(I_\mathrm{tail}\) here; the actual tail current will be smaller, since the bias branch \(M_6\) also draws current. This is fine for a first sanity check, as it tells us the slewing contribution is negligible even if the real value turns out several times larger.

This leaves plenty of margin for additional small-signal settling due to the limited bandwidth, as well as for reducing the supply current.

This also checks out.

8.3 Small-Signal Analysis of the OTA

Small-Signal Analysis of the OTA

• dc voltage gain \(A_0\)
• gain-bandwidth product (GBW)
• output noise

In order to size the OTA components we need to derive how the MOSFET parameters define the performance. The important small-signal metrics are

Small-Signal Analysis of the OTA

For a voltage follower in the configuration shown in Figure 33 the voltage gain is given by (see Figure 33) \[ (V_\mathrm{in} - V_\mathrm{out}) \cdot A_0 = V_\mathrm{out} \to \frac{V_\mathrm{out}}{V_\mathrm{in}} = \frac{A_0}{1 + A_0}. \tag{14}\]

The specification for GBW is directly given in Table 2, while the dc gain we have to calculate from the voltage accuracy specification.

So in order to reach an output voltage accuracy of at least 3% we need a dc gain of \(A_0 > 30.2\,\text{dB}\). To allow for process and temperature variation we need to add a bit of extra gain as margin.

Small-Signal Analysis of the OTA

Small-Signal vs. Large-Signal Operation

In order to get the correct dc voltage per the specification we require the large-signal gain calculated with Equation 14. However, calculating the large-signal gain of a circuit is quite involved (usually mandating the use of a large-signal nonlinear model for the used components), so we typically resort to do a simpler small-signal calculation instead, like in Section 8.3. We deliberately introduce this error, but we should not get confused about the difference between large- and small-signal operation!

8.3.1 OTA Small-Signal Transfer Function

• We assume that \(g_\mathrm{m1,2} = g_\mathrm{m1} = g_\mathrm{m2}\), \(g_\mathrm{m3,4} = g_\mathrm{m3} = g_\mathrm{m4}\), and \(C_\mathrm{gs3,4} = C_\mathrm{gs3} = C_\mathrm{gs4}\) for symmetry reasons (as \(M_1\) and \(M_2\) will have to be equally sized, as well as \(M_3\) and \(M_4\)).
• We will set \(g_\mathrm{mb}= 0\) for all MOSFETs.

In order to derive the governing small-signal equations for the OTA we will make a few simplifications:

OTA Small-Signal Transfer Function

• We will further set \(C_\mathrm{gd}= 0\) for all MOSFETs except for \(M_4\) where we expect a Miller effect on this capacitor, and we could add its effect by increasing the capacitance at the gate node of \(M_{3,4}\) (for background please see Section 17.1). However, as this does not create a dominant pole in this circuit, we consider this a minor effect (see Equation 17). Thus, only \(2C_\mathrm{gs3,4}\) is considered at the gate node of the current mirror load.

OTA Small-Signal Transfer Function

• We assume \(g_\mathrm{m}\gg g_\mathrm{ds}\), so we set \(g_\mathrm{ds1} = g_\mathrm{ds3} = 0\) as this node is dominated by \(g_\mathrm{m3}^{-1}\).
• The drain capacitance of \(M_2\) and \(M_4\), as well as the gate capacitance of \(M_2\), we could add to the load capacitance \(C_\mathrm{load}\) (see Figure 34). Do not dismiss this as a second-order correction: with the small \(C_\mathrm{load} = 50\,\text{fF}\) specified here, the sizing procedure will show that these device parasitics contribute roughly as much again as the specified load itself, so they effectively halve the achievable bandwidth if ignored.

The resulting small-signal equivalent circuit is shown in Figure 35.

OTA Small-Signal Transfer Function

Refresh MOSFET Small-Signal Model

Please review the MOSFET small-signal equivalent model in Figure 6 at this point. For the PMOS just flip the model upside-down.

OTA Small-Signal Transfer Function

Figure 35: 5-transistor OTA open-loop small-signal model.

5-transistor OTA open-loop small-signal model. For the closed-loop model, the input voltage \(V_\mathrm{in,n}\) is connected to the output voltage \(V_\mathrm{out}\). Note that the blue current source can be replaced by a conductance of \(g_\mathrm{m3,4}\).

OTA Small-Signal Transfer Function

Figure 36: 5-transistor OTA small-signal model with further simplifications.

We can further simplify Figure 35 by realizing that we operate the circuit purely differential and thus the tail point of \(M_1\) and \(M_2\) can be treated like a virtual ground, we thus short \(g_\mathrm{ds5}\). Therefore, we can move \(g_\mathrm{ds2} + g_\mathrm{ds4}\) in parallel to \(C_\mathrm{load}\). The current source \(g_\mathrm{m3,4} V_\mathrm{gs3}\) is replaced with the equivalent conductance \(g_\mathrm{m3,4}\). All the previous steps result in the further simplified equivalent circuit shown in Figure 36.

OTA Small-Signal Transfer Function

Realizing that \(V_\mathrm{gs1} = V_\mathrm{in,p} = V_\mathrm{in}/2\) and \(V_\mathrm{gs2} = V_\mathrm{in,n} = - V_\mathrm{in}/2\) we can formulate KCL at the output node to \[ -g_\mathrm{m3,4} V_\mathrm{gs3} - g_\mathrm{m1,2} \left( - \frac{V_\mathrm{in}}{2} \right) - V_\mathrm{out} (g_\mathrm{ds2} + g_\mathrm{ds4} + s C_\mathrm{load}) = 0. \tag{15}\]

\[ V_\mathrm{gs3} = -g_\mathrm{m1,2} \frac{V_\mathrm{in}}{2} \frac{1}{g_\mathrm{m3,4} + 2 \cdot s C_\mathrm{gs3,4}}. \tag{16}\]

In the simplified circuit model in Figure 36, we can see that we have two poles in the circuit, one at the gate node of \(M_{3,4}\) and one at the output.

We further realize that

By combining Equation 15 and Equation 16 and after a bit of algebraic manipulation we arrive at

OTA Small-Signal Transfer Function

\[ A(s) = \frac{V_\mathrm{out}(s)}{V_\mathrm{in}(s)} = \frac{g_\mathrm{m1,2}}{2} \frac{2 \cdot g_\mathrm{m3,4} + 2 \cdot s C_\mathrm{gs3,4}}{(g_\mathrm{m3,4} + 2 \cdot s C_\mathrm{gs3,4}) (g_\mathrm{ds2} + g_\mathrm{ds4} + s C_\mathrm{load})}. \tag{17}\]

\[ A(s \to 0) = A_0 = \frac{g_\mathrm{m1,2}}{g_\mathrm{ds2} + g_\mathrm{ds4}} \tag{18}\]

When we inspect Equation 17 we can see that for low frequencies the (open-loop) gain is

which is plausible, and confirms the requirement of a high impedance at the output node.

Above the dominant pole, but still well below the current-mirror doublet, the numerator of Equation 17 is still dominated by the term \(2 g_\mathrm{m3,4}\), and the gain becomes

OTA Small-Signal Transfer Function

\[ A(s) \approx \frac{g_\mathrm{m1,2}}{2} \frac{2 g_\mathrm{m3,4}}{g_\mathrm{m3,4} \cdot s C_\mathrm{load}} = \frac{g_\mathrm{m1,2}}{s C_\mathrm{load}} \tag{19}\]

\[ f_\mathrm{ug} = \frac{g_\mathrm{m1,2}}{2 \pi C_\mathrm{load}} \tag{20}\]

which is essentially the behavior of an integrator. This is the frequency range in which the amplifier is actually operated, so we use Equation 19 to calculate the frequency where the gain drops to \(|A(s_\mathrm{ug})| = 1 = g_\mathrm{m1,2} / | j \omega_\mathrm{ug} C_\mathrm{load}|\):

Note that this is exactly the dc gain Equation 18 multiplied by the dominant-pole frequency Equation 22, i.e. the gain-bandwidth product, as it has to be for a system that behaves like a single-pole system up to \(f_\mathrm{ug}\). The output conductances cancel, so the achievable GBW is set by \(g_\mathrm{m1,2}\) and \(C_\mathrm{load}\) alone.

OTA Small-Signal Transfer Function

Watch the Asymptote You Use

It is tempting to obtain \(f_\mathrm{ug}\) from the asymptote of Equation 17 for \(s \to \infty\), where both numerator and denominator are dominated by their \(s C_\mathrm{gs3,4}\) terms:

\[ A(s \to \infty) = \frac{g_\mathrm{m1,2}}{2 \cdot s C_\mathrm{load}} \tag{21}\]

OTA Small-Signal Transfer Function

Watch the Asymptote You Use

This differs from Equation 19 by a factor of two, and would predict a unity-gain frequency only half as large. The reason for the discrepancy is physical: Equation 21 describes the behavior above the doublet, where \(C_\mathrm{gs3,4}\) shorts out the current mirror so that the signal path through \(M_{3,4}\) is lost and only the direct path through \(M_2\) remains — hence half the transconductance. In a sensible design the doublet sits far above \(f_\mathrm{ug}\), so Equation 19 is the asymptote to use.

OTA Small-Signal Transfer Function

Looking at Equation 17, we see that we have a dominant pole at \(s_\mathrm{p}\) and a pole-zero doublet with \(s_\mathrm{pd}\)/\(s_\mathrm{zd}\): \[ s_\mathrm{p} = -\frac{g_\mathrm{ds2} + g_\mathrm{ds4}}{C_\mathrm{load}} \tag{22}\] \[ s_\mathrm{pd} = -\frac{g_\mathrm{m3,4}}{2 \cdot C_\mathrm{gs3,4}} \tag{23}\] \[ s_\mathrm{zd} = -\frac{g_\mathrm{m3,4}}{C_\mathrm{gs3,4}} \tag{24}\]

OTA Small-Signal Transfer Function

Why a Pole-Zero Doublet?

Looking at Equation 23 and Equation 24 we see that this pair is intimately linked by the same parameters and can only move together. Hence we call it a “doublet”. The effects of pole-zero doublets on the frequency response and settling time of OTAs can be found in (Kamath et al. 1974). This paper shows that doublets may cause severe degradation of settling time while only causing minor changes in the frequency response of the amplifier.

8.3.2 OTA Noise

For the noise analysis we ignore the pole-zero doublet due to \(C_\mathrm{gs3,4}\) (we assume minor impact due to this, hence we set \(C_\mathrm{gs3,4} = 0\)) and just consider the dominant pole given by Equation 22 due to the load capacitance. For the noise analysis at the output we set the positive input signal to ground and connect the output to the negative input, and thus starting from Figure 36 we arrive at the adapted small-signal circuit shown in Figure 37.

OTA Noise

Figure 37: 5-transistor OTA small-signal model for noise calculation (added noise sources shown in blue).

OTA Noise

Figure 38: 5-transistor OTA simplified small-signal model for noise calculation.

For symmetry reasons we can set \(\overline{I_\mathrm{n1,2}^2} = \overline{I_\mathrm{n1}^2} = \overline{I_\mathrm{n2}^2}\) and \(\overline{I_\mathrm{n3,4}^2} = \overline{I_\mathrm{n3}^2} = \overline{I_\mathrm{n4}^2}\). We see that we can replace the current source \(g_\mathrm{m1,2} V_\mathrm{gs2}\) with its equivalent conductance of \(g_\mathrm{m1,2}\), and this conductance is in parallel to \(g_\mathrm{ds2} + g_\mathrm{ds4}\), hence \(g_\mathrm{m1,2} + g_\mathrm{ds2} + g_\mathrm{ds4} \approx g_\mathrm{m1,2}\). The resulting simplified small-signal noise equivalent circuit is shown in Figure 38.

OTA Noise

We see that \[ \overline{V_\mathrm{gs3}^2} = \frac{1}{g_\mathrm{m3,4}^2} \left( \overline{I_\mathrm{n1}^2} + \overline{I_\mathrm{n3}^2} \right). \]

OTA Noise

Noise Addition

Remember that uncorrelated noise quantities need to be power-summed (i.e., \(I^2 = I_1^2 + I_2^2\))!

OTA Noise

We can then sum the total output noise current \(\overline{I_\mathrm{n}}\) as \[ \overline{I_\mathrm{n}^2} = \overline{I_\mathrm{n2}^2} + \overline{I_\mathrm{n4}^2} + g_\mathrm{m3,4}^2 \frac{1}{g_\mathrm{m3,4}^2} \left( \overline{I_\mathrm{n1}^2} + \overline{I_\mathrm{n3}^2} \right) = 2 \left( \overline{I_\mathrm{n1,2}^2} + \overline{I_\mathrm{n3,4}^2} \right). \]

The output noise voltage is then (using Equation 1)

OTA Noise

\[ \begin{split} \overline{V_\mathrm{n,out}^2}(f) &= \frac{\overline{I_\mathrm{n}^2}}{\left| g_\mathrm{m1,2} + s C_\mathrm{load} \right|^{2}} = \frac{\overline{I_\mathrm{n}^2}}{g_\mathrm{m1,2}^2 + (2 \pi f C_\mathrm{load})^2} \\ &= \frac{8 k T (\gamma_{1,2} g_\mathrm{m1,2} + \gamma_{3,4} g_\mathrm{m3,4})}{g_\mathrm{m1,2}^2 + (2 \pi f C_\mathrm{load})^2}. \end{split} \]

We can use the identity Equation 9 to calculate the rms output noise to

OTA Noise

\[ V_\mathrm{n,out,rms}^2 = \int_0^\infty \overline{V_\mathrm{n,out}^2}(f) \cdot df = \frac{k T}{C_\mathrm{load}} \left( 2 \gamma_{1,2} + 2 \gamma_{3,4} \frac{g_\mathrm{m3,4}}{g_\mathrm{m1,2}} \right). \tag{25}\]

Inspecting Equation 25 we can see that the integrated output noise is the \(k T / C\) noise of the output load capacitor, enhanced by the \(\gamma_{12}\) of the input differential pair, plus a (smaller) contribution of the current mirror load \(M_{3,4}\). Intuitively, this result makes sense. We learn that to reduce the output noise we should set \(g_\mathrm{m3,4} < g_\mathrm{m1,2}\).

OTA Noise

Exercise: Derivation of 5T-OTA Performance

Please take your time and carefully go through the explanations and derivations for the 5-transistor-OTA in Section 8.2 and Section 8.3. Try to do the calculations yourself; if you get stuck, review the previous chapters. There are additional useful derivations in Section 18.

8.4 5T-OTA Sizing

5T-OTA Sizing

\[ V_\mathrm{ds,sat} = \frac{2}{g_\mathrm{m}/I_\mathrm{D}} \tag{26}\]

Armed with the governing equations derived in Section 8.3, we can now size the MOSFETs in the OTA. We remember that we have to size \(M_{1,2}\) and \(M_{3,4}\) equally.

First, we need to select a proper \(g_\mathrm{m}/I_\mathrm{D}\) for the MOSFET. Remembering Section 3, we see that for the input differential pair we should go for a large \(g_\mathrm{m}\), thus we select a \(g_\mathrm{m}/I_\mathrm{D}= 10\). As \(g_\mathrm{ds}\) of \(M_2\) could limit the dc gain (Equation 18), we go with a rather long \(L = 5\,\mu\text{m}\). For current sources, a small \(g_\mathrm{m}/I_\mathrm{D}\) is a good idea, so we start with \(g_\mathrm{m}/I_\mathrm{D}=5\) (because we cannot go too low because of \(V_\mathrm{ds,sat}\)) and also an \(L = 5\,\mu\text{m}\). The \(g_\mathrm{m}/I_\mathrm{D}\) is also useful to estimate the required drain-source voltage to keep a MOSFET in saturation (i.e., keep the \(g_\mathrm{ds}\) small) with this approximate relationship:

5T-OTA Sizing

Exercise: 5T-OTA Sizing

Please size the 5T-OTA according to the previous \(g_\mathrm{m}/I_\mathrm{D}\) and \(L\) suggestions. Please calculate the \(W\) of \(M_{1-6}\) and the total supply current. Please check whether gain error, total output noise, and turn-on settling are met with the calculated devices sizes and bias currents.

5T-OTA Sizing

Solution: 5T-OTA Sizing

Sizing for Basic 5T-OTA

Copyright 2024-2025 Harald Pretl

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0

# read table data
from pygmid import Lookup as lk
import numpy as np
lv_nmos = lk('sg13_lv_nmos.mat')
lv_pmos = lk('sg13_lv_pmos.mat')
# list of parameters: VGS, VDS, VSB, L, W, NFING, ID, VT, GM, GMB, GDS, CGG, CGB, CGD, CGS, CDD, CSS, STH, SFL
# if not specified, minimum L, VDS=max(vgs)/2=0.9 and VSB=0 are used 

# define the given parameters as taken from the specification table or inital guesses
c_load = 50e-15
gm_id_m12 = 10
gm_id_m34 = 5
gm_id_m56 = 5
l_12 = 5
l_34 = 5
l_56 = 5
f_bw = 10e6 # -3dB bandwidth of the voltage buffer
i_total_limit = 10e-6
i_bias_in = 20e-6
output_voltage = 1.3
vin_min = 0.7
vin_max = 0.9
vdd_min = 1.45
vdd_max = 1.55

# we get the required gm of M1/2 from the -3dB bandwidth requirement of the voltage buffer specification
# note that the -3dB bandwidth of the voltage buffer with gain Av=1 is equal to the unity gain bandwidth
# of the ota, hence we set them equal here
# the unity-gain frequency of the 5T-OTA is f_ug = gm12 / (2*pi*C_load)
# on top of the bare specification we apply a design margin of:
#   3x for PVT variation plus the additional MOSFET parasitic loading
#   2x of reserve on dc gain and settling (the power budget allows for it)
bw_margin = 3 * 2
gm_m12 = bw_margin * 2*np.pi * f_bw * c_load
print('gm12 =', round(gm_m12/1e-3, 4), 'mS')

gm12 = 0.0188 mS

# since we know gm12 and the gmid we can calculate the bias current
id_m12 = gm_m12 / gm_id_m12
i_total = 2*id_m12
print('i_total (exact) =', round(i_total/1e-6, 1), 'µA')
# we round to 0.5µA bias currents
i_total = max(round(i_total / 1e-6 * 2) / 2 * 1e-6, 0.5e-6)
id_m12 = i_total/2

print('i_total (rounded) =', i_total/1e-6, 'µA')
if i_total < i_total_limit:
    print('[info] power consumption target is met!')
else:
    print('[info] power consumption target is NOT met!') 

i_total (exact) = 3.8 µA
i_total (rounded) = 4.0 µA
[info] power consumption target is met!

# we calculate the dc gain
gm_gds_m12 = lv_nmos.lookup('GM_GDS', GM_ID=gm_id_m12, L=l_12, VDS=0.75, VSB=0)
gm_gds_m34 = lv_pmos.lookup('GM_GDS', GM_ID=gm_id_m34, L=l_34, VDS=0.75, VSB=0)

gds_m12 = gm_m12 / gm_gds_m12
gm_m34 = gm_id_m34 * i_total/2
gds_m34 = gm_m34 / gm_gds_m34

a0 = gm_m12 / (gds_m12 + gds_m34)
print('a0 =', round(20*np.log10(a0), 1), 'dB')

a0 = 34.8 dB

# we calculate the MOSFET capacitance which adds to Cload, to see the impact on the BW
gm_cgs_m12 = lv_nmos.lookup('GM_CGS', GM_ID=gm_id_m12, L=l_12, VDS=0.75, VSB=0)
gm_cdd_m12 = lv_nmos.lookup('GM_CDD', GM_ID=gm_id_m12, L=l_12, VDS=0.75, VSB=0)
gm_cdd_m34 = lv_pmos.lookup('GM_CDD', GM_ID=gm_id_m34, L=l_34, VDS=0.75, VSB=0)

c_load_parasitic = abs(gm_m12/gm_cgs_m12) + abs(gm_m12/gm_cdd_m12) + abs(gm_m34/gm_cdd_m34)
print('additional load capacitance =', round(c_load_parasitic/1e-15, 1), 'fF')

f_bw = gm_m12 / (2*np.pi * (c_load + c_load_parasitic))
print('unity gain bandwidth incl. parasitics =', round(f_bw/1e6, 2), 'MHz')

additional load capacitance = 54.9 fF
unity gain bandwidth incl. parasitics = 14.3 MHz

# we can now look up the VGS of the MOSFET
vgs_m12 = lv_nmos.look_upVGS(GM_ID=gm_id_m12, L=l_12, VDS=0.75, VSB=0.0)
vgs_m34 = lv_pmos.look_upVGS(GM_ID=gm_id_m34, L=l_34, VDS=0.75, VSB=0.0) 
vgs_m56 = lv_nmos.look_upVGS(GM_ID=gm_id_m56, L=l_56, VDS=0.75, VSB=0.0) 

print('vgs_12 =', round(float(vgs_m12), 3), 'V')
print('vgs_34 =', round(float(vgs_m34), 3), 'V')
print('vgs_56 =', round(float(vgs_m56), 3), 'V')

vgs_12 = 0.367 V
vgs_34 = 0.729 V
vgs_56 = 0.591 V

# calculate settling time due to slewing with the calculated bias current
t_slew = (c_load + c_load_parasitic) * output_voltage / i_total
print('slewing time =', round(t_slew/1e-6, 3), 'µs')
t_settle = 5/(2*np.pi*f_bw)
print('settling time =', round(t_settle/1e-6, 3), 'µs')

slewing time = 0.034 µs
settling time = 0.056 µs

# calculate voltage gain error
gain_error = a0 / (1 + a0)
print('voltage gain error =', round((gain_error-1)*100, 1), '%')

voltage gain error = -1.8 %

# calculate total rms output noise
sth_m12 = lv_nmos.lookup('STH_GM', VGS=vgs_m12, L=l_12, VDS=0.75, VSB=0) * gm_m12
gamma_m12 = sth_m12/(4*1.38e-23*300*gm_m12)

sth_m34 = lv_pmos.lookup('STH_GM', VGS=vgs_m34, L=l_34, VDS=0.75, VSB=0) * gm_m34
gamma_m34 = sth_m34/(4*1.38e-23*300*gm_m34)

output_noise_rms = np.sqrt(1.38e-23*300 / (c_load + c_load_parasitic) * (2*gamma_m12 + 2*gamma_m34 * gm_m34/gm_m12))
print('output noise =', round(output_noise_rms/1e-6, 1), 'µVrms')

output noise = 354.2 µVrms

# calculate all widths
id_w_m12 = lv_nmos.lookup('ID_W', GM_ID=gm_id_m12, L=l_12, VDS=vgs_m12, VSB=0)
w_12 = id_m12 / id_w_m12
w_12_round = max(round(w_12*2)/2, 0.5)
print('M1/2 W =', round(w_12, 2), 'um, rounded W =', w_12_round, 'um')

id_m34 = id_m12
id_w_m34 = lv_pmos.lookup('ID_W', GM_ID=gm_id_m34, L=l_34, VDS=vgs_m34, VSB=0)
w_34 = id_m34 / id_w_m34
w_34_round = max(round(w_34*2)/2, 0.5) 
print('M3/4 W =', round(w_34, 2), 'um, rounded W =', w_34_round, 'um')

id_w_m5 = lv_nmos.lookup('ID_W', GM_ID=gm_id_m56, L=l_56, VDS=vgs_m56, VSB=0)
w_5 = i_total / id_w_m5
w_5_round = max(round(w_5*2)/2, 0.5)
print('M5 W =', round(w_5, 2), 'um, rounded W =', w_5_round, 'um')
w_6 = w_5_round * i_bias_in / i_total
w_6_round = max(round(w_6*2)/2, 0.5)
print('M6 W =', round(w_6_round, 2), 'um')

M1/2 W = 1.77 um, rounded W = 2.0 um
M3/4 W = 1.64 um, rounded W = 1.5 um
M5 W = 0.74 um, rounded W = 0.5 um
M6 W = 2.5 um

# print out final design values
print('5T-OTA dimensioning:')
print('--------------------')
print('M1/2 W=', w_12_round, ', L=', l_12)
print('M3/4 W=', w_34_round, ', L=', l_34)
print('M5   W=', w_5_round, ', L=', l_56)
print('M6   W=', w_6_round, ', L=', l_56)
print()
print('5T-OTA performance summary:')
print('---------------------------')
print('supply current =', round(i_total/1e-6, 1), 'µA')
print('output noise =', round(output_noise_rms/1e-6, 1), 'µVrms')
print('voltage gain error =', round((gain_error-1)*100, 1), '%')
print('unity gain bandwidth incl. parasitics =', round(f_bw/1e6, 2), 'MHz')
print('turn-on time (slewing+settling) =', round((t_slew+t_settle)/1e-6, 3), 'µs')
print()
print('5T-OTA bias point check:')
print('------------------------')
print('headroom M1 =', round(vdd_min-vgs_m34+vgs_m12-vin_max, 3), 'V')
print('headroom M4 =', round(vdd_min-vin_max, 3), 'V')
print('headroom M5 =', round(vin_min-vgs_m12, 3), 'V')

5T-OTA dimensioning:
--------------------
M1/2 W= 2.0 , L= 5
M3/4 W= 1.5 , L= 5
M5   W= 0.5 , L= 5
M6   W= 2.5 , L= 5

5T-OTA performance summary:
---------------------------
supply current = 4.0 µA
output noise = 354.2 µVrms
voltage gain error = -1.8 %
unity gain bandwidth incl. parasitics = 14.3 MHz
turn-on time (slewing+settling) = 0.09 µs

5T-OTA bias point check:
------------------------
headroom M1 = 0.188 V
headroom M4 = 0.55 V
headroom M5 = 0.333 V

The sizing procedure and its calculation are best performed in a Jupyter notebook, as we can easily look up the exact data from the pre-computed tables:

8.5 5T-OTA Simulation

5T-OTA Simulation

Exercise: 5T-OTA Design and Testbench

Please design the circuit of the 5T-OTA. Put the OTA circuit in a separate schematic, create a symbol for it, and use this symbol in a testbench you create in Xschem for this 5T-OTA used as a voltage buffer as shown in Figure 33. Use typical conditions for the simulation and check how well the specification in Table 2 is met and how well the derivations in Section 8.2 and Section 8.3 fit to the simulation results.

With the initial sizing of the MOSFETs of the 5T-OTA done, we can design the 5T-OTA circuit and set up a simulation testbench to check the performance parameters. Since this is the first time we draw a more complex schematic, and use a hierarchical design, we should note that drawing a schematic is an art, and there exists a set of rules and recommendations how to name pins, how to use annotations, and so on. Please read Section 22 before you start into your design work.

5T-OTA Simulation

Exercise: 5T-OTA Design and Testbench

If you get stuck, you can find the testbench and 5T-OTA schematic here (for the small-signal analysis) and here (for the large-signal settling simulation). For interested students, the loop gain analysis with Middlebrook’s and Tian’s method of the 5T-OTA can be found here. A comprehensive technical white paper by Texas Instruments about operational amplifier stability theory and compensation methods can be found in (Kay and Wells 2025).

8.6 Component Mismatch

8.6.1 MOSFET Mismatch

• A variation of the threshold voltage (mainly due to variations in doping levels).
• A variation of the critical dimensions of the MOSFET (\(W\) and \(L\) as well as vertical dimensions).

So far, we have assumed that implemented MOSFETs show no difference from device to device, which means that two transistors behave completely identical, and the resulting differential circuits are fully symmetric. However, due to manufacturing tolerances, this is not the case in reality. MOSFETs will show mismatch due to tiny random fluctuations in manufacturing, and we have to account for this. The mismatch parameters for various components are summarized in Table 4.

For a typical MOSFET, we usually consider two main mismatch effects (Pelgrom et al. 1989):

Both effects influence the drain current of the MOSFET, and they are indirectly proportional to the size of the MOSFET. So, if we want to reduce the mismatch, we have to increase the size of the MOSFET by increasing its gate area \(W \cdot L\).

If we formulate the drain current mismatch standard deviation \(\sigma\left\{\Delta I_\mathrm{D}/ I_\mathrm{D}\right\}\) of two nominally identical MOSFET we get

MOSFET Mismatch

\[ \sigma\left\{\frac{\Delta I_\mathrm{D}}{I_\mathrm{D}}\right\} = \frac{A_\mathrm{mosfet}}{\sqrt{W L}} \tag{27}\]

with \(A_\mathrm{mosfet}\) being a mismatch parameter for a given CMOS technology and \(\sigma\left\{\cdot\right\}\) being the standard deviation of the parameter in parentheses.

MOSFET Mismatch

MOSFET Mismatch

Usually, the mismatch in MOSFETs is characterized via two mismatch parameters (Pelgrom et al. 1989):

• The threshold voltage mismatch standard deviation

\[ \sigma\left\{\Delta V_\mathrm{th}\right\} = \frac{A_\mathrm{vth}}{\sqrt{W L}} \tag{28}\]

• and standard deviation of the size mismatch

\[ \sigma\left\{\frac{\Delta (W/L)}{(W/L)}\right\} = \frac{A_\mathrm{k}}{\sqrt{W L}}. \tag{29}\]

The resulting standard deviation of the input offset voltage \(V_\mathrm{offs}\) of a differential pair with small \(g_\mathrm{m}/I_\mathrm{D}\) is then given by (Razavi 2017) \[ \sigma\left\{V_\mathrm{offs}\right\} = \sqrt{\left( \frac{V_\mathrm{GS}- V_\mathrm{th}}{2} \right)^2 \cdot \sigma^2\left\{\frac{\Delta (W/L)}{{(W/L)}}\right\} + \sigma^2\left\{\Delta V_\mathrm{th}\right\}}. \tag{30}\]

The mismatch in the drain current of two current-mirror transistors, characterized as the standard deviation and for small \(g_\mathrm{m}/I_\mathrm{D}\), is given by (Razavi 2017)

\[ \sigma^2\left\{\frac{\Delta I_\mathrm{D}}{I_\mathrm{D}}\right\} = \sigma^2\left\{\frac{\Delta (W/L)}{(W/L)}\right\} + 4 \cdot \sigma^2\left\{\frac{\Delta V_\mathrm{th}}{V_\mathrm{GS}- V_\mathrm{th}}\right\}. \tag{31}\]

MOSFET Mismatch

MOSFET Mismatch

To minimize the input offset voltage in a differential pair we should strive to minimize the overdrive voltage \(V_\mathrm{GS}- V_\mathrm{th}\) (i.e., to maximize \(g_\mathrm{m}/I_\mathrm{D}\), see Equation 30) and to minimize the mismatch in current mirrors we should target a large overdrive voltage (i.e., to minimize \(g_\mathrm{m}/I_\mathrm{D}\), see Equation 31). In both cases the MOSFET area \(W \cdot L\) needs to be large enough (see Equation 28 and Equation 29).

Mismatch: Design Rules

• Mismatch shrinks with gate area: \(\sigma\left\{\Delta V_\mathrm{th}\right\} = A_\mathrm{vth}/\sqrt{W L}\)
• Differential pair: small overdrive (high \(g_\mathrm{m}/I_\mathrm{D}\)) for low offset
• Current mirror: large overdrive (low \(g_\mathrm{m}/I_\mathrm{D}\)) for accurate currents
• Verify with Monte Carlo simulation (\(N \approx 250\) runs)

MOSFET Mismatch

Number of Monte Carlo Simulation Runs

The number of Monte Carlo simulation runs \(N\) has to be large enough to approach Gaussian distributions to allow estimation of the variances. However, this comes at the cost of a large simulation time, so a balance has to be found. Often, \(N = 250\) is a good compromise between simulation time and well-behaved parameter distributions.

How can we now cope with mismatch in design and simulation? We can account for the transistor mismatch according to Equation 28 and Equation 29 in circuit analysis and quantify its effect. We can then take this into account when performing the circuit sizing procedure.

We can also simulate the effects of MOSFET mismatch on circuit performance by doing a Monte Carlo simulation. Here, a random realization of the variations of all circuit components (where mismatch is modelled) is taken and the circuit is simulated. Then, another random realization is simulated, and so on. In summary, we run the same simulation for different realizations \(N\) times and evaluate the resulting variations of the circuit parameters. If \(N\) is large enough, then the distributions should approach a Gaussian distribution, and we can then estimate the variances of the circuit parameters. Using statistical analysis we can then assess the yield of a circuit, i.e., how many circuit realizations will meet the specification.

8.6.2 Resistor Mismatch

\[ \sigma\left\{\frac{\Delta R}{R}\right\} = \frac{A_\mathrm{res}}{\sqrt{W L}} \tag{32}\]

As you can see in the previous discussion, running Monte Carlo simulations is a tedious process due to the large number of involved simulations and the required data processing of the heaps of simulation data. Luckily, CACE supports this type of simulation, and we will use it in Section 8.7.

Similar to the MOSFET mismatch discussed in Section 8.6.1, resistors will also show mismatch. Equivalently to Equation 27 the standard deviation of the resistor mismatch \(\sigma\left\{\Delta R / R\right\}\) can be characterized by

with \(A_\mathrm{res}\) being a mismatch parameter for a given CMOS technology.

With Equation 32 we now have two criteria for how to select the width \(W\) of a specific resistor (the length \(L\) is then derived from the required resistance value with \(R = R_\square \cdot L / W\)):

Resistor Mismatch

1. The current handling capability (the larger the \(W\), the more dc current a resistor can carry), and
2. the resistor mismatch (the larger the \(W\), the larger the \(W L\) for a given \(L/W\)).

If a resistor’s dimensions are not limited by the two criteria above then we usually choose the minimum width that is allowed for a given resistor in a specific technology (for SG13G2 it is \(W_\mathrm{min} = 0.5\,\mu\text{m}\)) to save area and to minimize the parasitic capacitance of the resistor to substrate.

8.6.3 Capacitor Mismatch

\[ \sigma\left\{\frac{\Delta C}{C}\right\} = \frac{A_\mathrm{cap}}{\sqrt{W L}} \tag{33}\]

Similar to the resistor matching discussed in Section 8.6.2, capacitors will also show mismatch. Equivalently to Equation 27 the standard deviation of the capacitor mismatch \(\sigma\left\{\Delta C / C\right\}\) can be characterized by

8.7 5T-OTA Simulation versus PVT and MC

5T-OTA Simulation versus PVT and MC

1. The supply voltage of the circuit has tolerances, and thus we need to check the performance against this variation.
2. The temperature at which the circuit is operated is likely changing. Also the performance against this has to be verified.

As you have seen in Section 8.5 running simulations by hand is tedious. When we want to check the overall performance, we have to run many simulations over various conditions:

5T-OTA Simulation versus PVT and MC

3. When manufacturing the wafers random variations in various process parameters lead to changed parameters of the integrated circuit components. In order to check for this effect, wafer foundries provide model files which shall cover these manufacturing excursions. Simplified, this leads to a slower or faster MOSFET, and usually NMOS and PMOS are not correlated, so we have the process corners SS, SF, TT, FS, and FF.

5T-OTA Simulation versus PVT and MC

3. So far, we have only used the TT models in our simulations.

The variations listed in the previous list are abbreviated as PVT (process, voltage, temperature) variations. In order to finalize a circuit all combinations of these (plus the variations in operating conditions like input voltage) have to be simulated. As you can imagine, this leads to a huge number of simulations and simulation results that have to be evaluated for pass/fail.

There are two options how to tackle this efficiently:

5T-OTA Simulation versus PVT and MC

1. As an experienced designer you have a very solid understanding of the circuit, plus based on the analytic equations you can identify which combination of operating conditions will lead to a worst case performance. Thus, you can drastically reduce the number of corners to simulate, and you run them by hand.
2. You are using a framework which highly automates this task of running a plethora of different simulations and evaluating the outcome. These frameworks are called simulation runners.

Luckily, there are open-source versions of simulation runners available, and we will use CACE in this lecture. CACE is written in Python and allows one to set up a datasheet in YAML that defines the simulation problem and the performance parameters to evaluate against specified limits. The resulting simulations are then run in parallel and the simulation data is evaluated and summarized in various forms.

There is a CACE setup available for our 5T-OTA. The datasheet describes the operating conditions and the simulations tasks. For each simulation a testbench template is needed, this one is used for ac simulations, this one is used for noise simulation, and this one is used for transient simulation.

5T-OTA Simulation versus PVT and MC

Running CACE Simulation

The CACE simulation run can be started with

cace cace/voltage-buffer-ota.yaml

The simulation results are then placed into the cace/_docs folder. If in addition to the default Markdown report an HTML output is needed for easier review then using Pandoc it can be easily converted and viewed with with

cace/cace_view.sh cace/_docs/ota-5t_schematic.md

5T-OTA Simulation versus PVT and MC

Note 2: CACE Summary for 5T-OTA

CACE Summary for ota-5t

netlist source: schematic

Parameter	Tool	Result	Min Limit	Min Value	Typ Target	Typ Value	Max Limit	Max Value	Status
Output voltage ratio	ngspice	gain	0.97 V/V	0.987 V/V	any	1.000 V/V	1.03 V/V	1.007 V/V	Pass ✅
Bandwidth	ngspice	bw	10e6 Hz	15550400.000 Hz	any	26912100.000 Hz	any	34052200.000 Hz	Pass ✅
Output voltage ratio (MC)	ngspice	gain_mc	any	0.998 V/V	any	0.999 V/V	any	1.001 V/V	Pass ✅
Bandwidth (MC)	ngspice	bw_mc	10e6 Hz	24312600.000 Hz	any	26806900.000 Hz	any	28104300.000 Hz	Pass ✅
Output noise	ngspice	noise	any	0.308 mV	any	0.371 mV	1 mV	0.454 mV	Pass ✅
Settling time	ngspice	tsettle	any	0.137 us	any	0.144 us	10 us	0.156 us	Pass ✅

Plots

gain_vs_temp

gain_vs_temp

After a successful run, a documentation is automatically generated. The result of a full run of this OTA design is presented here:

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

gain_vs_vin

gain_vs_vin

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

gain_vs_vdd

gain_vs_vdd

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

gain_vs_corner

gain_vs_corner

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

bw_vs_temp

bw_vs_temp

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

bw_vs_vin

bw_vs_vin

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

bw_vs_vdd

bw_vs_vdd

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

bw_vs_corner

bw_vs_corner

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

gain_mc

gain_mc

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

bw_mc

bw_mc

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

noise_vs_temp

noise_vs_temp

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

noise_vs_vin

noise_vs_vin

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

noise_vs_vdd

noise_vs_vdd

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

noise_vs_corner

noise_vs_corner

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

settling_vs_temp

settling_vs_temp

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

settling_vs_vin

settling_vs_vin

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

settling_vs_vdd

settling_vs_vdd

5T-OTA Simulation versus PVT and MC

CACE Summary for 5T-OTA

settling_vs_corner

settling_vs_corner

8.7.1 PVT Simulation Analysis

Looking at the CACE report in Note 2, we see that (luckily) the specification is met across all PVT corners. This is great news! We now have a design that we carefully simulated across PVT and other corners and that is ready for layout. Once we have the layout ready, we can extract the wiring parasitics (\(R\) and \(C\)) as well as other layout-dependent effects like well proximity. Using this augmented netlist, we can then again use CACE to check performance across conditions and parameter variations, and if we still pass all specification points, then our design is finished.

8.7.2 Monte Carlo Simulation Analysis

The Monte Carlo run in the same CACE report in Note 2 tells a different story: here the output voltage specification is not met, due to MOSFET mismatch! Note that this is not a contradiction to the PVT result above — PVT corners shift all devices together, whereas mismatch makes nominally identical devices differ, and it is exactly this asymmetry that the voltage buffer is sensitive to. We have not considered transistor mismatch in the circuit sizing procedure, and as a result the selected MOSFET dimensions prove to be too small. We should now go back and change the transistor sizing (increasing \(L\) significantly while keeping the \(g_\mathrm{m}/I_\mathrm{D}\) values). Likely we will find that some performance parameters are now deteriorating due to the increased MOSFET dimensions, and we need to iterate until all performance metrics are met in the presence of transistor mismatch.

It is not unusual that the power consumption now increases, as we have to increase the size of the MOSFETs for matching, and these larger MOSFETs increase the parasitic capacitances which in turn lead to larger power consumption to keep the required bandwidth by increasing the \(g_\mathrm{m}\).

Monte Carlo Simulation Analysis

Exercise: Re-Sizing of 5T-OTA for Mismatch

Go back to Section 8.4 and repeat the sizing procedure of the 5T-OTA by increasing the \(L\) of the MOSFETs significantly. Focus first on the differential pair as it will likely have the biggest impact (see Equation 30). Then, tune the size of the output current mirror if necessary (see Equation 31).

Once you are happy with the sizing result, repeat the PVT simulations in CACE to confirm the performance of the voltage buffer including mismatch.

8.8 OTA Variants

OTA Variants

Figure 39: Single-ended OTA with rail-to-rail output stage.

Following, we are going to discuss two popular variants of the simple 5T-OTA. The first version provides an almost rail-to-rail single-ended output and can thus be used for a variety of applications requiring this range. The arrangement is shown in Figure 39. It is a single-stage amplifier, as the only high-impedance point is at the output where significant voltage-gain is produced. The current mirrors can be used to scale up the current generated in the input differential pair to some extent in the output stage (or can be used to lower the current compared to the bias current in the diffpair); i.e., the bias currents of the input stage and the output stage can be set independently.

Being a single-stage amplifier stability is usually not an issue, as only the output node is high-ohmic; all other nodes feature a MOSFET diode so the node impedance is \(\approx g_\mathrm{m}^{-1}\) and thus the according poles are located at high frequencies.

OTA Variants

Figure 40: Single-ended two-stage OTA with rail-to-rail output.

Another popular version is shown in Figure 40. Here, we have a two-stage amplifier able to provide higher voltage gain. The first stage (the diffpair loaded by a current mirror) is followed by a single-stage common-source amplifier with current-source load. Being a two-stage amplifier with two high-ohmic nodes, stability is a concern, so usually we need some form of compensation. Figure 40 shows a very simplistic Miller-compensation (see Section 13.1) using \(C_\mathrm{M}\). Often, we would want to implement a more advanced scheme. Some examples can be found in (Baker, n.d.). An interesting technique is the indirect compensation with cascoded input differential pairs (see Figure 58) for higher power supply rejection. An advantage of this two-stage amplifier (compared with the simple 5T-OTA) is that both output nodes of the input stage are dc-balanced: each of them sits one \(V_\mathrm{GS}\) below \(V_\mathrm{DD}\) — on the left set by the diode-connected \(V_\mathrm{GS3}\), on the right set by the gate of the second-stage device \(M_5\), i.e. by \(V_\mathrm{GS5}\). In the plain 5T-OTA the right-hand node is instead the output node, whose dc level is imposed by the external feedback, so the two sides of the differential pair are generally not balanced.

OTA Variants

Figure 41: A basic low-dropout voltage regulator (LDO) with Miller compensation.

Note that the circuit of Figure 40 can be easily modified into a low-dropout voltage regulator (LDO). This simple yet often effective circuit is shown in Figure 41. The pass transistor \(M_\mathrm{pass}\) has to be sized according to the load current and the dropout voltage.

OTA Variants

\[ V_\mathrm{out} \approx V_\mathrm{ref} \left( 1 + \frac{R_1}{R_2} \right) \]

The reference voltage \(V_\mathrm{ref}\) is scaled by \(R_1\) and \(R_2\) so that the output voltage \(V_\mathrm{out}\) is given by

if the gain of the OTA is sufficiently high. The quiescent current through \(R_{1,2}\) establishes a minimum load current for the LDO, which is often good for stability. More information on LDOs can be found in (Razavi 2019).

References

Baker, R. J. n.d. “Bad Circuit Design 3 - Compensating an Op-Amp.” https://cmosedu.com/cmos1/bad_design/bad_design3/bad_design_3.htm.

Gray, Paul R., Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer. 2009. Analysis and Design of Analog Integrated Circuits. Wiley.

Kamath, B. Y. T., R. G. Meyer, and P. R. Gray. 1974. “Relationship Between Frequency Response and Settling Time of Operational Amplifiers.” IEEE Journal of Solid-State Circuits 9 (6): 347–52. https://doi.org/10.1109/JSSC.1974.1050527.

Kay, A., and C. Wells. 2025. “Technical White Paper - Operational Amplifier Stability Theory and Compensation Methods.” Texas Instruments. https://www.ti.com/lit/wp/sboa626/sboa626.pdf.

Murmann, Boris. 2013. Analysis and Design of Elementary MOS Amplifier Stages. NTS Press.

Pelgrom, M. J. M., A. C. J. Duinmaijer, and A. P. G. Welbers. 1989. “Matching Properties of MOS Transistors.” IEEE Journal of Solid-State Circuits 24 (5): 1433–39. https://doi.org/10.1109/JSSC.1989.572629.

Razavi, Behzad. 2017. Design of Analog CMOS Integrated Circuits. McGraw-Hill.

Razavi, Behzad. 2019. “The Low Dropout Regulator [A Circuit for All Seasons].” IEEE Solid-State Circuits Magazine 11 (2): 8–13. https://doi.org/10.1109/mssc.2019.2910952.

References