Transistor Sizing Using gm/ID Methodology

Analog (Integrated) Circuit Design

3 Transistor Sizing Using gm/ID Methodology

Transistor Sizing Using gm/ID Methodology

MOSFET Square-Law Model

One of the many simplifications of the square-law model is that the mobility of the charge carriers is assumed constant (it is not). Further, the existence of a threshold voltage is assumed, but in fact this voltage exists only given a certain definition, and depending on definition, its value changes. In addition, in nm CMOS, the threshold voltage is a function of many things, like \(W\) and \(L\).

When designing integrated circuits it is an important question how to select various parameters of a MOSFET, like \(W\), \(L\), or the bias current \(I_\mathrm{D}\). In comparison to using discrete components in PCB design, or also compared to a bipolar junction transistor (BJT), we have these degrees of freedom, which make integrated circuit design so interesting.

Often, transistor sizing in entry-level courses is based on the square-law model, where a simple analytical equation for the drain current can be derived. However, in nanometer CMOS, the MOSFET behavior is much more complex than these simple models. Also, these highly simplified derivations introduce concepts like the threshold voltage or the overdrive voltage, which are interesting from a theoretical viewpoint, but have little practical use.

3.1 MOSFET Characterization Testbench

An additional shortcoming of the square-law model is that it is only valid in strong inversion, i.e. for large \(V_\mathrm{GS}\) where the drain current is dominated by the drift current. As soon as the gate-source voltage gets smaller, the square-law model breaks, as the drain current component based on diffusion currents gets dominant. Modern compact MOSFET models (like the PSP model used in SG13G2) use hundreds of parameters and fairly complex equations to somewhat properly describe MOSFET behavior over a wide range of parameters like \(W\), \(L\), and temperature. A modern approach to MOSFET sizing is thus based on the thought to use exactly these MOSFET models, characterize them, put the resulting data into tables and charts, and thus learn about the complex MOSFET behavior and use it for MOSFET sizing.

Being a well-established approach we select the \(g_\mathrm{m}/I_\mathrm{D}\) methodology introduced by (Silveira et al. 1996) and extended in (Jespers and Murmann 2017). A brief introduction is available here as well.

The \(g_\mathrm{m}/I_\mathrm{D}\) methodology has the huge advantage that it catches MOSFET behavior quite accurately over a wide range of operating conditions, and the curves look very similar for pretty much all CMOS technologies, from micrometer bulk CMOS down to nanometer FinFET devices. Of course the absolute values change, but the method applies universally.

MOSFET Characterization Testbench

Note on Characterization Testbench

The testbenches are relatively straightforward, with one exception: The drain current noise is sensed via the drain voltage source vd and converted to a noise voltage (node n) using a current-controlled voltage source (CCVS). This is necessary as the .noise simulation statement works with voltages.

In order to get the required tabulated data we use a testbench in Xschem which sweeps the length \(L\) and the terminal voltages (\(V_\mathrm{GS}\), \(V_\mathrm{DS}\) and \(V_\mathrm{SB}\)) for a fixed device width \(W = 5\,\text{µm}\) and records various large- and small-signal parameters, which are then stored in large tables. The testbench for the LV NMOS is shown in Figure 10, and the TB for the LV PMOS is shown in Figure 11.

MOSFET Characterization Testbench

Figure 10: Testbench for LV NMOS \(g_\mathrm{m}/I_\mathrm{D}\) characterization.

MOSFET Characterization Testbench

Figure 11: Testbench for LV PMOS \(g_\mathrm{m}/I_\mathrm{D}\) characterization.

MOSFET Characterization Testbench

Note on width \(W\)

In general, the device width could be included as a fifth sweep variable. However, this is not necessary since the parameters scale approximately linearly with \(W\) across the typical range encountered in analog design. For \(W > 2\,\text{µm}\) the error lies within about 1.5% for \(g_\mathrm{m}/I_\mathrm{D}\), \(g_\mathrm{m}/g_\mathrm{ds}\) and \(g_\mathrm{m}/C_\mathrm{gg}\) as described in (Jespers and Murmann 2017).

We will use Jupyter notebooks to inspect the resulting data, and interpret some important graphs. This will greatly help to understand the MOSFET behavior.

MOSFET Characterization Testbench

Figure 12: Overview of the \(g_\mathrm{m}/I_\mathrm{D}\) MOSFET characterization procedure (Dorrer 2025).

The resulting four-dimensional data is saved into a .txt file and imported into two Jupyter notebooks as visualized in Figure 12. The first notebook outputs .mat files, which are compatible with the pygmid Python package used for sizing. The second notebook generates vector graphic characterization plots, which are shown in Section 3.2 for LV NMOS and Section 3.3 for LV PMOS. With these plots, an immediate understanding of the tradeoffs for the given transistor can be acquired. Furthermore, they can be used for fast hand calculations in small circuits.

3.2 NMOS Characterization in Saturation

NMOS Characterization in Saturation

Power Consumption

Designing for minimum power consumption is pretty much always mandated. For battery-operated equipment it is a paramount requirement, but also in other equipment electrical energy consumption is a concern, and often severely limited by the cooling capabilities of the electrical system.

First, we will start looking at the LV NMOS. In Section 3.3 we have the corresponding graphs for the LV PMOS. In this lecture, we will only use the LV MOSFETs. While there are also the HV types available, they are mainly used for high-voltage circuits, like circuits connecting to the outside world. Here, we only will design low-voltage circuits running at a nominal supply voltage of \(1.5\,\text{V}\), so only the LV types are of interest to us.

In the plots that follow we will set \(V_\mathrm{DS}= V_\mathrm{DD}/2\) to keep the MOSFET in saturation (as this is the region of operation where most MOSFETs are operated when working in class-A). We will later also look at the MOSFET performance in triode operation, as this is the operation mode where the MOSFET is used as a switch. While the \(g_\mathrm{m}/I_\mathrm{D}\) method is primarily intended to be used for circuits where the MOSFETs are held in saturation and are biased by a certain bias current (usually referred to class-A), the generated tables using the testbenches of Section 3.1 contain the data for all MOSFET bias points.

The first important graph is the plot of \(g_\mathrm{m}/I_\mathrm{D}\) and \(f_\mathrm{T}\) versus the gate-source voltage \(V_\mathrm{GS}\). First let us answer the question why \(g_\mathrm{m}/I_\mathrm{D}\) is a good parameter to look at, and actually this is also the central parameter in the \(g_\mathrm{m}/I_\mathrm{D}\) methodology. In many circuits we want to get a large amplification from a MOSFET, which corresponds to a large \(g_\mathrm{m}\). We want to achieve this by spending the minimum biasing current possible (ideally zero), as we almost always design for lowest power consumption. Thus, a high \(g_\mathrm{m}/I_\mathrm{D}\) ratio is good.

NMOS Characterization in Saturation

Note that \[ \frac{g_\mathrm{m}}{I_\mathrm{D}} = \frac{1}{n V_\mathrm{T}} \tag{3}\] for a MOSFET in weak inversion (i.e., small gate-source voltage).

For the classical square-law model of the MOSFET in strong inversion, \(g_\mathrm{m}/I_\mathrm{D}\) is given as \[ \frac{g_\mathrm{m}}{I_\mathrm{D}} = \frac{2}{V_\mathrm{GS}- V_\mathrm{th}} = \frac{2}{V_\mathrm{od}} \tag{4}\] with \(V_\mathrm{th}\) the threshold voltage and \(V_\mathrm{od}\) the so-called “overdrive voltage.” The latter is sometimes also dubbed the effective gate-source voltage \(V_\mathrm{eff}\) (Carusone et al. 2011).

However, as can be seen in the below plot, there exists a strong and unfortunate trade-off with device speed, characterized here by the transit frequency \(f_\mathrm{T}\). It would be ideal if there exists a design point where we get high transconductance per bias current concurrently to having the fastest operation, but unfortunately, this is clearly not the case. The \(g_\mathrm{m}/I_\mathrm{D}\) peaks for \(V_\mathrm{GS}< 0.3\,\text{V}\), and the highest speed we get at \(V_\mathrm{GS}\approx 1.2\,\text{V}\). The dashed vertical line plots the nominal threshold voltage, as you can see in this continuum of parameter space, it marks not a particularly special point.

\(n\) is the subthreshold slope, and \(V_\mathrm{T} = k T / q\) which is \(25.8\,\text{mV}\) at \(300\,\text{K}\).

We thus have \(n \approx 1.38\) for this LV NMOS, which falls nicely into the usual range for \(n\) of \(1.3\) to \(1.5\) for bulk CMOS (FinFET have \(n\) very close to \(1\)).

NMOS Characterization in Saturation

Why 300 K?

Why are we so often using a temperature of \(300\,\text{K}\) for a typical condition? As this corresponds to roughly \(27^{\circ}\text{C}\), this accounts for some self heating compared to otherwise cooler usual room temperatures. Further, engineers like round numbers which are easy to remember, so \(300\,\text{K}\) is used as a proxy for room temperature.

NMOS Characterization in Saturation

As we can also see from the plot below, the peak transit frequency of the LV NMOS is about \(75\,\text{GHz}\), which allows building radio-frequency circuits up to ca. \(f_\mathrm{T} / 10 = 7.5\,\text{GHz}\), which is a respectable number. It is no coincidence that the transition for RF design in the GHz-range switched from BJT-based technologies to CMOS roughly in the time frame when 130nm CMOS became available (ca. 2000).

Note that \(f_\mathrm{T}\) saturates and even decreases again at around \(V_\mathrm{GS}= 1.2\,\text{V}\) due to second-order effects of the transistor like velocity saturation and DIBL. Velocity saturation describes the effect that the drift velocity of the electrons (or holes) no longer increases once the lateral electric field along the channel becomes large, which in a short channel already happens at moderate \(V_\mathrm{DS}\). As a consequence, also \(g_\mathrm{m}\) saturates. Since \(f_\mathrm{T} \propto g_\mathrm{m}/ C_\mathrm{gg}\), \(f_\mathrm{T}\) can not further increase. DIBL describes the effect where a high \(V_\mathrm{DS}\) lowers the potential barrier at the source, effectively reducing the threshold voltage. Additionally, at high \(V_\mathrm{GS}\) the channel is confined to a narrow region at the surface, leading to more carrier scattering and thus lower mobility (vertical-field mobility degradation).

The following figure plots \(f_\mathrm{T}\) against \(g_\mathrm{m}/I_\mathrm{D}\) for several different \(L\). As you can see, device speed maximizes for a low \(g_\mathrm{m}/I_\mathrm{D}\) and a short \(L\). Note that the drain-source voltage is kept at \(V_\mathrm{DS}= 0.75\,\text{V} = V_\mathrm{DD}/ 2\), which is a typical value keeping the MOSFET in saturation across the characterization sweeps. Further, the source-bulk voltage is kept at \(V_\mathrm{SB}= V_\mathrm{S} - V_\mathrm{B} = 0\,\text{V}\), which means bulk and source terminals are connected. If \(V_\mathrm{SB}\neq 0\,\text{V}\), then the so-called body effect, bulk effect or back-gate effect occurs.

If \(V_\mathrm{SB}> 0\,\text{V}\), then \(V_\mathrm{th}\) increases. If \(V_\mathrm{SB}< 0\,\text{V}\), then \(V_\mathrm{th}\) decreases. At first glance, this effect may sound unwanted (and often also is), however, improved circuit designs by changing the bulk potential can be realized. For example, circuit 16 in (Pretl and Eberlein 2021) shows an implementation of a current mirror by exploiting the body effect. However, keep in mind that a deep-n-well (DNW), also called triple-well, is needed for NMOS transistors when the bulk is not tied to GND. This DNW may not be supported by the used PDK or can add additional costs to the wafer processing.

NMOS Characterization in Saturation

The next plot shows the ratio of \(g_\mathrm{m}/ g_\mathrm{ds}\) versus \(g_\mathrm{m}/I_\mathrm{D}\). The ratio \(g_\mathrm{m}/ g_\mathrm{ds}\) is the so-called “self-gain” of the MOSFET, and shows the maximum voltage gain we can achieve in a single transistor configuration. As one can see the self gain increases for increasing \(L\), but this also gives a slower transistor, so again there is a trade-off. This plot allows us to select the proper \(L\) of a MOSFET if we know which amount of self gain we need.

NMOS Characterization in Saturation

The following figure plots the drain current density \(I_\mathrm{D}/W\) as a function of \(g_\mathrm{m}/I_\mathrm{D}\) and \(L\). With this plot we can find out how to set the \(W\) of a MOSFET once we know the biasing current \(I_\mathrm{D}\), the \(L\) (selected according to self gain, \(f_\mathrm{T}\), and other considerations) and the \(g_\mathrm{m}/I_\mathrm{D}\) design point we selected. The drain current density \(I_\mathrm{D}/W\) is a very useful normalized metric to use, because the physical action in the MOSFET establishes a charge density in the channel below the gate, and the changing of the \(W\) of the device merely transforms this charge density into an absolute parameter (together with \(L\)).

NMOS Characterization in Saturation

The following plot shows the minimum drain-source voltage \(V_\mathrm{ds,sat}\) that we need to establish in order to keep the MOSFET in saturation. As you can see, this value is almost independent of \(L\), and increases for small \(g_\mathrm{m}/I_\mathrm{D}\). So for low-voltage circuits, where headroom is precious, we tend to bias at \(g_\mathrm{m}/I_\mathrm{D}\ge 10\), whereas for fast circuits we need to go to small \(g_\mathrm{m}/I_\mathrm{D}\le 5\) requiring substantial voltage headroom per MOSFET stage that we stack on top of each other.

NMOS Characterization in Saturation

For analog circuits the noise performance is usually quite important. Thermal noise of a resistor (the Johnson-Nyquist noise) has a flat power-spectral density (PSD) given by \(\overline{V_\mathrm{n}^2}/\Delta f = 4 k T R\), where \(k\) is Boltzmann’s constant, \(T\) absolute temperature, and \(R\) the value of the resistor (the unit of \(\overline{V_\mathrm{n}^2}/\Delta f\) is \(\text{V}^2/\text{Hz}\)). This PSD is essentially flat until very high frequencies where quantum effects start to kick in.

NMOS Characterization in Saturation

Noise Notation

We usually leave the \(\Delta f\) away for a shorter notation, so we write \(\overline{V_\mathrm{n}^2}\) when we actually mean \(\overline{V_\mathrm{n}^2}/\Delta f\). In case of doubt look at the unit of a quantity, whether it shows \(\text{V}^2\) or \(\text{V}^2/\text{Hz}\) or \(\text{V}/\sqrt{\text{Hz}}\) (or \(\text{A}^2\) or \(\text{A}^2/\text{Hz}\) or \(\text{A}/\sqrt{\text{Hz}}\)).

NMOS Characterization in Saturation

Noise Notation

Please also note that the pair of \(k T\) pretty much always shows up together, so when you do a calculation and you miss the one or the other, that is often a sign for miscalculation. Boltzmann’s constant \(k = 1.38 \cdot 10^{-23}\,\text{J/K}\) is just a scaling factor from thermal energy expressed as a temperature \(T\) to energy \(E = k T\) expressed in Joule.

NMOS Characterization in Saturation

Noise Notation

Further, when working with PSD there is the usage of a one-sided (\(0 \le f < \infty\)) or two-sided power spectral density (PSD) (\(-\infty < f < \infty\)). The default in this lecture is the usage of the one-sided PSD.

NMOS Characterization in Saturation

In this lecture the only MOSFET noise we consider is the drain noise (as discussed in Section 2.1.2), showing up as a current noise between drain and source. For a realistic MOSFET noise model, also a (correlated) gate noise component and the thermal noise of the gate resistance needs to be considered.

The factor \(\gamma\) (Equation 1) is a function of many things (in classical theory, \(\gamma = 2/3\) in saturation and \(\gamma = 1\) in triode), and it is characterized in the following plot as a function of \(g_\mathrm{m}/I_\mathrm{D}\) and \(L\). So when calculating MOSFET noise we can lookup \(\gamma\) in the below plot, and use Equation 1 to calculate the effective drain current noise.

In a MOSFET, unfortunately, besides the thermal noise according to Equation 1, there is also a substantial low-frequency excess noise, called “flicker noise” due to its characteristic \(\overline{I_\mathrm{d,nf}^2} = K_\mathrm{f}/f\) behavior (this means that this noise PSD decreases versus frequency). In order to characterize this flicker noise the following plot shows the cross-over frequency \(f_\mathrm{co}\), where the flicker noise is as large as the thermal noise. As can be seen in the below plot, this frequency is a strong function of \(L\) and \(g_\mathrm{m}/I_\mathrm{D}\). Generally, the flicker noise is proportional to \((W L)^{-1}\), so the larger the device is, the lower the flicker noise. The parameter \(g_\mathrm{m}/I_\mathrm{D}\) largely stays constant when we keep \(W/L\) constant, so for a given \(g_\mathrm{m}/I_\mathrm{D}\) flicker noise is proportional to \(1/L^2\). However, increasing \(L\) lowers device speed dramatically, so here we have a trade-off between flicker-noise performance and MOSFET speed, and this can have dramatic consequences for high-speed circuits.

NMOS Characterization in Saturation

MOSFET Flicker Noise

The physical origin of flicker noise is the crystal interface between silicon (Si) and the silicon dioxide (SiO₂). Since these are different materials, there are dangling bonds, which can capture charge carriers traveling in the channel. After a random time, these carriers are released, and flicker noise is the result. The amount of flicker noise is a function of the manufacturing process, and will generally be different between device types and wafer foundries.

NMOS Characterization in Saturation

As you can see in the following plot, \(f_\mathrm{co}\) can reach well into the 10’s of MHz for short MOSFETs, significantly degrading the noise performance of a circuit.

During the design phase, it might be convenient to have an overview of the most relevant sizing plots of the NMOS on one page. This overview can be downloaded here.

3.3 PMOS Characterization in Saturation

PMOS Characterization in Saturation

PMOS Sign Convention

In all PMOS plots we plot positive values for voltages and currents, to have compatible plots to the NMOS. Of course, in a PMOS, voltages and currents have different polarity compared to the NMOS.

In the following, we have the same plots as discussed in Section 3.2, but now for the PMOS.

PMOS Characterization in Saturation

\(g_\mathrm{m}/I_\mathrm{D}\) and \(f_\mathrm{T}\) versus the gate-source voltage \(V_\mathrm{GS}\):

\(f_\mathrm{T}\) against \(g_\mathrm{m}/I_\mathrm{D}\) for several different \(L\). One can see a significantly lower top speed for the PMOS compared to the NMOS, which means for high-speed circuits the NMOS should be used. The reason for this is the approximately two to three times higher mobility of electrons compared to the mobility of holes.

PMOS Characterization in Saturation

\(g_\mathrm{m}/ g_\mathrm{ds}\) versus \(g_\mathrm{m}/I_\mathrm{D}\). Unfortunately, one can see a modelling error for the PMOS in this plot. The self gain \(g_\mathrm{m}/ g_\mathrm{ds}\) reaches non-physical values, which indicates an issue with the \(g_\mathrm{ds}\) modelling for the PMOS. We can not use these values for our circuit sizing, so we will use the respective NMOS plots also for the PMOS.

PMOS Characterization in Saturation

Beware of Modelling Issues

This example shows how important it is to benchmark the device models when starting to use a new technology. Modelling artifacts like the one shown are quite common, as setting up the device compact models and parametrize them according to measurement data is a very complex task. In any case, just be aware that modelling issues could exist in whatever PDK you are going to use!

PMOS Characterization in Saturation

Drain current density \(I_\mathrm{D}/W\) as a function of \(g_\mathrm{m}/I_\mathrm{D}\) and \(L\):

PMOS Characterization in Saturation

Minimum drain-source voltage \(V_\mathrm{ds,sat}\) versus \(g_\mathrm{m}/I_\mathrm{D}\) and \(L\):

PMOS Characterization in Saturation

Noise factor \(\gamma\) versus \(g_\mathrm{m}/I_\mathrm{D}\) and \(L\):

PMOS Characterization in Saturation

Flicker noise corner frequency \(f_\mathrm{co}\) versus \(g_\mathrm{m}/I_\mathrm{D}\) and \(L\). If you compare this figure carefully with the NMOS figure you can see that for some operating points the flicker noise for the PMOS is lower than for the NMOS. This is often true for CMOS technologies, so it can be an advantage to use a PMOS transistor in places where flicker noise is critical, like an OTA input stage. Using PMOS has the further advantage that the bulk node can be tied to source (which for NMOS is only possible in a triple-well technology, which is often not available), which gets rid of the body effect.

PMOS Characterization in Saturation

During the design phase, it might be convenient to have an overview of the most relevant sizing plots of the PMOS on one page. This overview can be downloaded here.

3.4 Tradeoffs in Saturation

Tradeoffs in Saturation

Figure 13: Overview of key design tradeoffs depending on the channel length \(L\) and transconductance efficiency \(g_\mathrm{m}/I_\mathrm{D}\) (Dorrer 2025).

In Figure 13, an overview of the tradeoffs mentioned above is presented. The design parameters are only shown once for their best-case implementation. Their worst-case value is then located at the opposite arrow. In conclusion, strong inversion with short channels is used for high-speed applications, whereas weak inversion with long channels is for low-power and low-noise applications. Moderate inversion with longer channels is used for current sources to maximize their output resistance. Note that the two arrows for strong inversion with long channels and weak inversion with short channels are empty since they make practically no sense. This tradeoff overview simplifies the choice of the starting \(g_\mathrm{m}/I_\mathrm{D}\) and \(L\) values in the sizing scripts.

3.5 NMOS and PMOS Characterization in Triode

NMOS and PMOS Characterization in Triode

• The resistance of the switch/MOSFET when it is turned on (\(R_\mathrm{on} = 1 / g_\mathrm{ds}\)).
• The shunt capacitance of the switch when it is turned off (\(C_\mathrm{off}\) is defined by the coupling capacitances between drain and source).

Besides using the MOSFET as a transconductor in saturation we often use the MOSFET as a switch in triode mode (to either switch voltages or currents). In this triode/switch mode of operation we are mainly interested in two parameters:

In the operation of the NMOS as a switch the gate is usually pulled to \(V_\mathrm{DD}\) and the bulk is permanently connected to \(V_\mathrm{SS}\) to achieve the lowest \(R_\mathrm{on}\) (to turn the switch off the gate is pulled towards \(V_\mathrm{SS}\)). Likewise, to turn on a PMOS, the gate is usually pulled to \(V_\mathrm{SS}\) and the bulk is connected to \(V_\mathrm{DD}\). In this situation the drain/source potential is somewhere between \(V_\mathrm{DD}\) and \(V_\mathrm{SS}\), so the MOSFET will experience a \(V_\mathrm{SB}\neq 0\), leading to a quite noticeable bulk effect. Once the drain/source potential is sufficiently high for NMOS (low PMOS) the switch resistance will drastically degrade.

In order to get a feeling for the behavior of the MOSFET as a switch the following characterization plots show \(R_\mathrm{on}\) and \(C_\mathrm{off}\) for the NMOS and the PMOS, respectively. Both plots are for \(L = L_\mathrm{min} = 0.13\mu m\), as for switches usually minimum length devices are used. Only for special applications (e.g., the drain-source leakage current in off-mode is a concern) MOSFETs with increased \(L\) are used.

NMOS and PMOS Characterization in Triode

As can be seen in the previous plot, an NMOS can be used to switch at potentials close to \(V_\mathrm{SS}\), while a PMOS is the better choice when switching at potentials close to \(V_\mathrm{DD}\). To construct a switch which can work for all voltage levels between \(V_\mathrm{DD}\) and \(V_\mathrm{SS}\) an NMOS is put in parallel to a PMOS, resulting in the well-known transmission gate.

NMOS and PMOS Characterization in Triode

As the switch on-resistance gets lower when increasing \(W\), the off-capacitance gets larger. Thus, a good performance indicator for comparing switches in a given technology is the \(R_\mathrm{on} C_\mathrm{off}\) product.

3.6 Tradeoffs in Triode

Tradeoffs in Triode

Figure 14: Overview of key design tradeoffs in switches depending on the channel width \(W\) and the channel length \(L\) (Dorrer 2025).

Some might think that sizing switches is a straightforward task, but in reality, they also come with several tradeoffs, and depending on the application, they can be incredibly complicated. The essential design parameters in switches are the on-resistance \(R_\mathrm{on}\), the off-capacitance \(C_\mathrm{off}\), the drain-source leakage current \(I_\mathrm{leak}\), and their impact on clock feedthrough and charge injection (Carusone et al. 2011). In Figure 14, an overview of the tradeoffs of these design parameters depending on the channel width \(W\) and the channel length \(L\) is presented. In conclusion, if \(W/L\) increases, \(R_\mathrm{on}\) decreases, and the switching speed increases. If \(W/L\) decreases, \(I_\mathrm{leak}\), \(C_\mathrm{off}\), and the drain-source overlap capacitance decrease, effectively reducing clock feedthrough and charge injection (Gray et al. 2009). Practically, it does not make sense to make the switch both wide and long.

References

Carusone, Tony C., David Johns, and Kenneth Martin. 2011. Analog Integrated Circuit Design. Wiley.

Dorrer, Simon. 2025. “An Open-Source Adaptive Event-Based ADC for Bio-Signal Acquisition in 130 Nm CMOS.” https://epub.jku.at/obvulihs/content/titleinfo/12118473?query=dorrer.

Gray, Paul R., Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer. 2009. Analysis and Design of Analog Integrated Circuits. Wiley.

Jespers, Paul G. A., and Boris Murmann. 2017. Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables. Cambridge University Press.

Pretl, Harald, and Matthias Eberlein. 2021. “Fifty Nifty Variations of Two-Transistor Circuits: A Tribute to the Versatility of MOSFETs.” IEEE Solid-State Circuits Magazine 13 (3): 38–46. https://iic-jku.github.io/fifty-nifty-circuits/.

Silveira, F., D. Flandre, and P. G. A. Jespers. 1996. “A g_m/I_D Based Methodology for the Design of CMOS Analog Circuits and Its Application to the Synthesis of a Silicon-on-Insulator Micropower OTA.” IEEE Journal of Solid-State Circuits 31 (9): 1314–19. https://doi.org/10.1109/4.535416.

References