Electrostatic Discharge and Latch-Up

Design of Complex Integrated Circuits

9 Electrostatic Discharge and Latch-Up

9.1 Electrostatic Discharge

This chapter covers two reliability hazards that every IC design must handle: electrostatic discharge (ESD), the sudden discharge of statically charged objects into the chip, and latch-up, the unwanted triggering of parasitic bipolar structures in CMOS. The treatment of ESD follows (Amerasekera and Duvvury 2002); overviews of ESD as a reliability concern, including protection structures, and of ESD test methods can be found in (Duvvury and Amerasekera 1993; Ker et al. 2001).

Electrostatic Discharge

• A thin isolation layer (like the gate oxide) may break down, leading to a low-resistance path between structures that should be isolated.
• Diodes, resistors, or wiring may melt while carrying the large discharge current, creating a short or an open.

When an external object at a high potential (e.g., charged by the triboelectric effect or by induction from an electric field) touches one of the connections of a circuit, the resulting electrostatic discharge produces a large transient voltage or current—for example, when ICs are handled by humans or by machines with faulty grounding. ESD can even occur without actual contact, as an arc across an air gap. Devices sustain two types of permanent damage as a result of ESD:

9.1.1 ESD Models for Testing

• The human-body model (HBM): a 100 pF capacitor discharged through 1.5 kΩ, modeling the touch of a charged person.
• The charged-device model (CDM): the IC itself is charged and discharges abruptly through a single pin, modeling machine handling.
• The machine model (MM): a 200 pF capacitor discharged with negligible series resistance, modeling charged (metallic) machinery (largely superseded by HBM/CDM testing today).

Three standardized models are used for ESD testing of ICs, differing in the equivalent charge storage and discharge path:

Each model defines the charging voltage of an equivalent capacitance and the discharge network—this defines the ESD pulse shape and the peak discharge voltage and current. An “HBM level of 1 kV” means the model capacitance is charged to 1 kV before the discharge. The equivalent circuit and the resulting pulse shapes are shown in Figure 80 and Figure 81: the HBM produces a comparatively long pulse (~150 ns decay) causing mostly thermal stress, while the CDM produces a very short (~1 ns) pulse with high current, leading to large on-chip voltage drops.

ESD Models for Testing

Figure 80: Equivalent circuit of the standardized ESD test models: the model capacitance \(C\) is charged to the test voltage via a high-ohmic resistor; closing the switch discharges it into the DUT through the model resistance \(R\).

Equivalent circuit of the standardized ESD test models: the model capacitance \(C\) is charged to the test voltage via a high-ohmic resistor; closing the switch discharges it into the DUT through the model resistance \(R\). HBM: \(C = 100\,\)pF, \(R = 1.5\,\)kΩ; MM: \(C = 200\,\)pF, \(R \approx 0\); CDM: the capacitance is the device itself against ground.

ESD Models for Testing

Figure 81: Typical discharge current waveforms of the ESD models (schematic representation): the 1 kV HBM pulse peaks at about 0.67 A (\(V/1.5\,\)kΩ) with a slow decay (\(\tau \approx 150\,\)ns), while the 500 V CDM pulse reaches several amperes within a fraction of a nanosecond and rings out within a few nanoseconds.

Typical discharge current waveforms of the ESD models (schematic representation): the 1 kV HBM pulse peaks at about 0.67 A (\(V/1.5\,\)kΩ) with a slow decay (\(\tau \approx 150\,\)ns), while the 500 V CDM pulse reaches several amperes within a fraction of a nanosecond and rings out within a few nanoseconds. Note the logarithmic time axis.

9.1.2 ESD Protection Concept

• The primary ESD element (typically a pair of large diodes to the rails, like \(D_{1,2}\), or a snapback device) provides the main low-ohmic path for a positive or negative ESD pulse.
• The series resistor \(R_\mathrm{in}\) (typically around 500 Ω) limits the current into the secondary protection, which clamps the voltage at the gate oxide of the input receiver.

In a CDM event, the charge stored in the body of the IC is discharged when some pin touches external ground; discharge currents of several amperes with rise times below a nanosecond are typical. HBM testing is standardized in ANSI/ESDA/JEDEC JS-001, CDM testing in JS-002.

All inputs and outputs of an IC (including \(V_\mathrm{DD}\) and \(V_\mathrm{SS}\)) have to be protected against ESD. The protection circuits are usually bundled in a pad library providing optimized I/O cells (digital input/output, analog input/output, RF input/output, supply pads). The protection elements are made from the devices available in the technology, optimized for high-current/high-voltage operation—usually they are provided and qualified by the wafer foundry.

Figure 82 shows the general protection scheme of a (bidirectional) digital I/O:

ESD Protection Concept

• The secondary protection (typically a gate-protected NMOS or a diode to the rails, like the shown \(D_{3,4}\)) clamps the voltage at the input of the receiver, protecting the gate oxide from ESD stress.
• The power clamp between \(V_\mathrm{DD}\) and \(V_\mathrm{SS}\) provides a discharge path between the rails, preventing an ESD-induced rise of the supply voltage from damaging core circuits.

ESD Protection Concept

• All diodes and clamps are reverse-biased (off) during normal operation. A positive ESD pulse at the pad is discharged via the upper diode and the power clamp to ground; a negative pulse is discharged via the lower diode.
• The receiver might implement additional functionality for the digital input, like Schmitt-trigger action or input filtering.

ESD Protection Concept

• The driver consists of large output devices (NMOS and PMOS) that provide the necessary drive strength for the digital output, while the series resistance and protection elements safeguard the driver during ESD events. Additional features might be a tri-state capability or slew-rate control. A (small) series resistance \(R_\mathrm{s}\) in the drain path helps divert the ESD current into the protection devices, at the cost of degrading the driver in normal operation.

ESD Protection Concept

• Often, this series resistance is implemented by extending the drain region of the MOSFETs and blocking the silicide (recall the OP layer from Section 4.2), the same ballasting technique used in the ggNMOS (Figure 83) described below.
• The layout of the protection elements is critical: they should be placed close to the pad to minimize parasitic inductance and resistance, ensuring a fast response to ESD events.

ESD Protection Concept

Figure 82: ESD protection of a bidirectional digital I/O pad: the primary diodes \(D_1\)/\(D_2\) carry the main discharge current to the rails, the series resistor \(R_\mathrm{in}\) limits the current into the secondary diodes \(D_3\)/\(D_4\), which protect the gate oxide of the input receiver; the output driver \(M_\mathrm{P}\)/\(M_\mathrm{N}\) is decoupled from the pad by the small drain series resistance \(R_\mathrm{s}\); the power clamp closes the discharge loop between \(V_\mathrm{DD}\) and \(V_\mathrm{SS}\).

ESD protection of a bidirectional digital I/O pad: the primary diodes \(D_1\)/\(D_2\) carry the main discharge current to the rails, the series resistor \(R_\mathrm{in}\) limits the current into the secondary diodes \(D_3\)/\(D_4\), which protect the gate oxide of the input receiver; the output driver \(M_\mathrm{P}\)/\(M_\mathrm{N}\) is decoupled from the pad by the small drain series resistance \(R_\mathrm{s}\); the power clamp closes the discharge loop between \(V_\mathrm{DD}\) and \(V_\mathrm{SS}\). All protection elements are off in normal operation.

9.1.3 Analog and RF Pads

• \(V_\mathrm{DD}\) and digital input-only/output-only pads: derived from the general I/O pad
• Analog pads: series resistances \(R_\mathrm{s}\), \(R_\mathrm{in}\) often prohibitive \(\rightarrow\) function-specific ESD protection
• RF pads: ESD protection is highly critical
  • often no series resistance acceptable
  • parasitic capacitance of the protection limits the bandwidth
  • RF I/Os often limit the ESD rating of an RFIC \(\rightarrow\) always custom-designed

\(V_\mathrm{DD}\) pads and digital input-only or output-only pads are easily derived from the general I/O pad shown in Figure 82. Analog input and output pads are more critical, since the series resistances (\(R_\mathrm{s}\), \(R_\mathrm{in}\)) might be prohibitive for the intended circuit function; usually, special ESD protection tailored to the specific function is designed for analog pins. For high-frequency pads, ESD protection is highly critical: often no series resistance is acceptable at all, and the protection elements add parasitic capacitance that limits the bandwidth of the I/O. Since the size of an ESD element is determined by the required low resistance and thermal dissipation, RF I/Os often limit the ESD rating of an RFIC, and RF ESD protection is always custom-designed (see, e.g., Ker et al. 2000).

9.1.4 Snapback Devices: The ggNMOS

• Gate tied to \(V_\mathrm{SS}\) \(\rightarrow\) NMOS off in normal operation
• Positive ESD event: drain-bulk junction breaks down (avalanche) and injects current into the substrate
• Drop across \(R_\mathrm{sub}\) forward-biases the source-bulk junction \(\rightarrow\) parasitic lateral NPN turns on
• Device snaps back to a low holding voltage and conducts the ESD current
• Silicide-blocked extended drain ballasts the current across the device width

A popular primary protection element is the grounded-gate NMOS (ggNMOS), shown in Figure 83. In normal operation, the NMOS is off, since its gate is tied to \(V_\mathrm{SS}\). During a positive ESD event, the drain-bulk diode breaks down (reversibly) by avalanche multiplication and injects current into the substrate; this current, together with the substrate resistance \(R_\mathrm{sub}\), forward-biases the source-bulk junction, turning on the parasitic lateral NPN transistor (drain = collector, bulk = base, source = emitter). The device “snaps back” to a low holding voltage and conducts the ESD current between drain and source. A silicide-blocked extended drain improves the robustness by ballasting the current across the device width.

Snapback Devices: The ggNMOS

Figure 83: The grounded-gate NMOS (ggNMOS) ESD protection device: (a) cross section with the parasitic lateral NPN (drain = collector, substrate = base, source = emitter) and the substrate resistance \(R_\mathrm{sub}\); the drain contact is set back from the gate with blocked silicide, forming a ballast resistance; (b) snapback I/V characteristic—after avalanche breakdown at \(V_\mathrm{t1}\), the parasitic NPN turns on and the device conducts the ESD current at a low holding voltage \(V_\mathrm{h}\).

9.1.5 RC-Triggered Power Clamp

• Normal operation: capacitor charged to \(V_\mathrm{DD}\), inverter output low, \(M_\mathrm{ESD}\) off
• ESD event: rail rises faster than the RC time constant \(\rightarrow\) inverter input stays low \(\rightarrow\) \(M_\mathrm{ESD}\) on, shorting the rails
• Beware: a fast \(V_\mathrm{DD}\) ramp at power-up can falsely trigger the clamp
• Inrush current \(I_\mathrm{rush} = C_\mathrm{decoup} \cdot dV_\mathrm{DD}/dt\) \(\rightarrow\) controlled supply ramp is essential

Figure 84 shows an RC-triggered supply clamp: during normal operation, the capacitor is charged to \(V_\mathrm{DD}\), the inverter output is low, and the large clamping NMOS \(M_\mathrm{ESD}\) is off. During a (positive) ESD event, the supply rail rises much faster than the RC time constant, the capacitor voltage cannot follow, the inverter input stays low, and its output turns \(M_\mathrm{ESD}\) on—providing a conducting path for the ESD current between the rails.

Beware that a fast \(V_\mathrm{DD}\) ramp during power-up can falsely trigger such a clamp! For this reason, when building the power supplies of electronic systems, designers often include additional circuitry to control the ramp rate or to temporarily disable the RC-triggered clamp during power-up. Considering also the potentially large inrush current \(I_\mathrm{rush} = C_\mathrm{decoup} \cdot dV_\mathrm{DD}/dt\), a controlled supply ramp during supply turn on is essential.

RC-Triggered Power Clamp

Figure 84: RC-triggered power-supply clamp: in normal operation, the capacitor is charged to \(V_\mathrm{DD}\), the inverter output is low, and the large clamp transistor \(M_\mathrm{ESD}\) is off.

RC-triggered power-supply clamp: in normal operation, the capacitor is charged to \(V_\mathrm{DD}\), the inverter output is low, and the large clamp transistor \(M_\mathrm{ESD}\) is off. During a fast ESD-induced rise of \(V_\mathrm{DD}\), the RC node lags behind, the inverter output goes high, and \(M_\mathrm{ESD}\) shorts the rails for the duration of the event.

9.1.6 The Silicon-Controlled Rectifier

\[ \beta_\mathrm{NPN} \cdot \beta_\mathrm{PNP} \geq 1 \tag{64}\]

A silicon-controlled rectifier (SCR, thyristor) can be formed in standard CMOS by utilizing the available diffusions (\(n^+\) and \(p^+\)) and wells (n-well and p-substrate/p-well), forming a PNPN structure, shown in Figure 85. The structure contains two cross-coupled parasitic bipolar transistors (a vertical PNP and a lateral NPN); if the loop gain of the two transistors satisfies

then the SCR triggers and provides a very low-ohmic path (snapback). Deliberately built SCRs are excellent ESD protection devices, but the same structure exists parasitically in every CMOS inverter—which brings us to latch-up.

The Silicon-Controlled Rectifier

Figure 85: The silicon-controlled rectifier (SCR) in CMOS: (a) the PNPN structure formed by the \(p^+\) anode diffusion, the n-well, the \(p\)-substrate, and the \(n^+\) cathode diffusion; (b) equivalent circuit of the two cross-coupled parasitic bipolar transistors—if their loop gain exceeds unity, the structure latches into a low-ohmic state.

9.1.7 ESD-Protected Areas

• Grounding of all conductors: benches, tools, equipment, chairs, and carts are bonded to a common ground point. The connections are deliberately dissipative rather than metallic (typically \(10^6 \ldots 10^9\,\Omega\)), so that charge bleeds off slowly instead of flowing as a fast, damaging current pulse.
• Personnel grounding: wrist straps (with an integrated 1 MΩ resistor for operator safety) at the bench, plus dissipative shoes and flooring while walking—walking across an insulating floor charges a person to several kV within a few steps.

On-chip protection is dimensioned for the standardized qualification levels (a few kV HBM, several hundred volts CDM); it does not make a chip immune to the tens of kilovolts that a person or a machine accumulates during handling. Everything outside the chip therefore has to be controlled as well: wafer test, assembly, board manufacturing, and laboratory work are carried out inside an ESD-protected area (EPA), as specified in IEC/EN 61340-5-1 and ANSI/ESD S20.20.

The principle of an EPA is simple: no ungrounded conductor and no charged insulator is allowed near an unprotected device, and all conductive objects—the operator included—are kept at the same potential, so that no discharge can occur in the first place:

ESD-Protected Areas

• Dissipative work surfaces and floors, avoiding both metal (discharge too fast) and plastic (charges up and cannot be discharged).
• Ionizers neutralize the insulators that cannot be grounded at all—plastic housings, PCB base material, documents, clothing—by blowing ionized air across the workplace.
• Humidity control (typically 40 … 60 % relative humidity) raises the surface conductivity of insulators and strongly reduces triboelectric charging; dry air in winter is a classic cause of field failures.

ESD-Protected Areas

• ESD-safe packaging: devices leave the EPA only inside shielding (Faraday) bags, conductive trays and tubes, or dissipative foam, and are unpacked only inside another EPA.
• Marking, training, and auditing: the EPA boundary is marked, wrist straps and mats are verified regularly (typically per shift), and personnel is trained—an EPA is a process, not just a set of equipment.

ESD-sensitive devices and their packaging carry the ESD susceptibility symbol, whereas the EPA boundary and the protective equipment itself carry the ESD protective symbol, shown in Figure 86.

ESD-Protected Areas

Figure 86: The two standardized ESD symbols: (a) the susceptibility symbol (a crossed-out hand in a triangle) marks ESD-sensitive devices, assemblies, and their packaging; (b) the protective symbol (a hand in a triangle under a protecting arc) marks EPA entrances and ESD-protective equipment such as wrist straps, mats, bags, and trays.

The two standardized ESD symbols: (a) the susceptibility symbol (a crossed-out hand in a triangle) marks ESD-sensitive devices, assemblies, and their packaging; (b) the protective symbol (a hand in a triangle under a protecting arc) marks EPA entrances and ESD-protective equipment such as wrist straps, mats, bags, and trays. A device carrying the symbol in (a) must only be unpacked inside an area marked with the symbol in (b).

9.2 Latch-Up

Latch-Up

Figure 87: Parasitic thyristor in a CMOS inverter, causing latch-up: the vertical PNP (PMOS source = emitter, n-well = base, substrate = collector) and the lateral NPN (NMOS source = emitter, substrate = base, n-well = collector) are cross-coupled through the well resistance \(R_\mathrm{well}\) and the substrate resistance \(R_\mathrm{sub}\).

Latch-up is the creation of a low-impedance path between the power-supply rails (\(V_\mathrm{DD}\) to \(V_\mathrm{SS}\)) by triggering the parasitic SCR formed by the complementary devices in CMOS, shown in Figure 87 and already discussed in Section 9.1.6. The vertical PNP (emitter = PMOS source in the n-well, base = n-well, collector = substrate) and the lateral NPN (emitter = NMOS source, base = substrate, collector = n-well) form a PNPN structure between the rails, with the well and substrate resistances \(R_\mathrm{well}\) and \(R_\mathrm{sub}\) completing the classic thyristor equivalent circuit.

Parasitic thyristor in a CMOS inverter, causing latch-up: the vertical PNP (PMOS source = emitter, n-well = base, substrate = collector) and the lateral NPN (NMOS source = emitter, substrate = base, n-well = collector) are cross-coupled through the well resistance \(R_\mathrm{well}\) and the substrate resistance \(R_\mathrm{sub}\). Injected charge that develops \(\approx 0.7\,\)V across either resistance triggers the loop.

Latch-Up

• Transient latch-up: the low-impedance state persists only while the stimulus is applied.
• True latch-up: the state remains after the stimulus is removed and can only be ended by a power-supply shutdown—use a current limit on the power supply when testing ICs in the lab! The large current can destroy the chip by overheating and electromigration.

Latch-up is triggered by a current or voltage stimulus on an input, output, or I/O pin (injecting carriers into wells or substrate), or by an over-voltage on the supply pin. Two cases are distinguished:

9.2.1 Latch-Up Testing

• Standard qualification test: JEDEC JESD78
• Current-limited pulse (typically 100 mA, 10 ms) applied to all pads
• Voltage compliance: 1.5× max. supply voltage above ground, defined negative value below ground
• Additional supply over-voltage test
• Supply current monitored after each stimulus \(\rightarrow\) latched state detected

Latch-up testing is a standard procedure during IC qualification (JEDEC JESD78): a current-limited (typically 100 mA), 10 ms pulse is applied to all pads, with the voltage compliance constrained to 1.5× the maximum supply voltage above ground and to a defined negative value below ground; additionally, a supply over-voltage test is applied. After each stimulus, the supply current is monitored to detect a latched state.

9.2.2 Latch-Up Prevention

• Physical separation of the diffusions/wells forming the parasitic BJTs lowers their current gain (shallow-trench isolation helps to increase the electrical distance without a large spacing penalty).
• Reduce the parasitic resistances \(R_\mathrm{well}\) and \(R_\mathrm{sub}\) that develop the triggering base-emitter voltages: place many well and substrate ties, and/or use an epi-process with a highly doped substrate.

Latch-up is prevented by weakening the parasitic bipolar transistors and their coupling:

Latch-Up Prevention

• Use guard rings around critical components (e.g., I/O drivers and any junction that may inject carriers) to collect stray charges before they can reach a parasitic base, as shown in Figure 88.

Latch-Up Prevention

Figure 88: Guard rings for latch-up prevention (layout top view): the NMOS is surrounded by a grounded \(p^+\) guard ring, the PMOS by an \(n^+\) guard ring tied to \(V_\mathrm{DD}\) inside the n-well.

Guard rings for latch-up prevention (layout top view): the NMOS is surrounded by a grounded \(p^+\) guard ring, the PMOS by an \(n^+\) guard ring tied to \(V_\mathrm{DD}\) inside the n-well. The rings collect injected minority and majority carriers before they can act as base current for the parasitic bipolar transistors.

Latch-Up Prevention

• For output buffers, the sources of the NMOS and PMOS have to be tied to \(V_\mathrm{SS}\) and \(V_\mathrm{DD}\) and their drains connected directly to the pad; guard rings (well and substrate ties) are required around every device directly tied to a pad, and double guard rings (an n-well isolator plus a \(p^+\) isolator) have to be placed between the n-channel and p-channel buffers, as well as between the buffers and the internal circuitry.

Adopting these design practices helps to significantly reduce the risk of latch-up in CMOS circuits.

Foundries cast these practices into their design rule manuals. IHP SG13G2, for example, dedicates Sec. 7.2 Latch-up Guidelines of the SG13G2 layout rules to the topic:

Latch-Up Prevention

• Rules LU.a and LU.b limit the maximum distance from any \(p^+\) active area inside the n-well to an n-well tie, and from any \(n^+\) active area inside the p-well to a substrate tie, to 20 µm—this is the rule-deck version of “place many well and substrate ties”.
• Rules LU.c to LU.d1 limit how far a tie may extend beyond its contact (6 µm), which keeps the resistance of the tie itself low.

In the open-source SG13G2 KLayout DRC decks, the latch-up rules are checked by default (since IHP-Open-PDK commit 3b393f31, March 2025): the maximal deck runs them unless latchUpRules is set to false, and the regular deck runs LU.b unless the precheck_drc option is set. Older versions of the layout-rule document still state otherwise, so check which rules your deck actually runs.

References

Amerasekera, Ajith, and Charvaka Duvvury. 2002. ESD in Silicon Integrated Circuits. 2nd ed. Wiley.

Duvvury, Charvaka, and Ajith Amerasekera. 1993. “ESD: A Pervasive Reliability Concern for IC Technologies.” Proceedings of the IEEE 81 (5): 690–702. https://doi.org/10.1109/5.220901.

Ker, Ming-Dou, Tung-Yang Chen, Chung-Yu Wu, and Hun-Hsien Chang. 2000. “ESD Protection Design on Analog Pin with Very Low Input Capacitance for High-Frequency or Current-Mode Applications.” IEEE Journal of Solid-State Circuits 35 (8): 1194–99. https://doi.org/10.1109/4.859509.

Ker, Ming-Dou, Jeng-Jie Peng, and Hsin-Chin Jiang. 2001. “ESD Test Methods on Integrated Circuits: An Overview.” IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2: 1011–14. https://doi.org/10.1109/ICECS.2001.957647.

References