The Layout

Design of Complex Integrated Circuits

4 The Layout

4.1 Files and Tapeout

The layout is the 2D representation of the IC manufacturing data. While the schematic captures the electrical intent of a design, the layout captures its physical realization: in the layout tools, the design is drawn on several layers, which are the foundation for the generation of the photomasks used in IC production. Commercial layout tools are, e.g., Cadence Virtuoso, Siemens L-Edit, and open-source tools are Magic and KLayout. The layers are usually manipulated before the geometries are transferred to the masks (shrink, enlarge, invert, combination of several layers into one mask layer, optical proximity correction, etc.).

4.2 Generic Layer Definition

The layout is checked for compliance with the wafer-fab design rules in the design rule check (DRC), and for conformance with the intended circuit in the layout-versus-schematic (LVS) check, where a netlist extracted from the layout is compared to the netlist of the original schematic. If all checks pass, the layout data is sent to mask production—this step is called tapeout. The mask house processes the layout data and produces the photomasks used by the wafer fab (depending on technology complexity, between 10 and 80 masks).

The standard file format for layout data is GDSII, a hierarchical database in a binary stream format. A newer format with more efficient storage is OASIS, but GDSII is still very common.

Generic Layer Definition

Table 8: Generic layer definition used in this text

Layer name	IHP SG13	Purpose
RX	Activ	\(n^+\) (RX) or \(p^+\) (RX in BP) diffusion regions (e.g., S/D of MOSFETs)
PC	GatPoly	Polysilicon gate
NW	NWell	\(n\)-well region
BP	pSD	\(p\)-implant marker (i.e., blocks the \(n\)-implant)
OP	SalBlock	Silicide blocking over PC and RX
CA	Cont	Contact (connects RX or PC to M1)
M1	Metal1	First-level metal
V1	Via1	Via connecting M1 to M2
M2	Metal2	Second-level metal
V2	Via2	Via connecting M2 to M3
M3	Metal3	Top metal, mostly aluminum, to facilitate wire-bond packages
PAD	Passiv	Opening in the passivation to contact the top metal for pads

Different foundries use different layer names. The layer names defined in Table 8 are quite typical for a basic CMOS process technology and are used for the remainder of the text; the corresponding IHP SG13 names are given for reference.

4.3 Devices

4.3.1 NMOS and PMOS Transistors

• The MOSFET is created by the intersection of RX and PC; this intersection defines \(W\) and \(L\) of the transistor. The areas of RX not covered by PC become the source and drain regions.
• Whether a device is NMOS or PMOS is decided by whether the RX shape is contained inside a BP region (RX plus BP is \(p^+\), RX without BP is \(n^+\)).
• A \(p^+\) substrate contact is created by drawing RX covered by BP (outside the n-well).
• An \(n^+\) well contact is created by drawing plain RX located inside NW.

Figure 41 shows the layout (mask top view) of an NMOS and a PMOS transistor. The following observations can be made:

NMOS and PMOS Transistors

• The NW must surround the PMOS with sufficient margin.
• The layer BP is a pure marking layer, assisting mask generation and device extraction from the layout.
• CA contacts connect source/drain/gate as well as the \(p^+\)/\(n^+\) contacts to M1.

NMOS and PMOS Transistors

Figure 41: Layout (mask top view) of an NMOS (left) and a PMOS transistor (right).

Layout (mask top view) of an NMOS (left) and a PMOS transistor (right). The transistor channel is formed where PC crosses RX; the BP marker turns the diffusion \(p^+\), and the NW well surrounds the PMOS. The area where PC overlaps RX is the actual transistor channel, defining its \(W\) and \(L\). Next to each transistor sits the corresponding substrate or well contact. Note that BP acts as a marking layer, whereas RX, PC, and NW define the actual device regions on the silicon.

4.3.2 Polysilicon Resistor

\[ R = \rho \frac{L}{t \cdot W} = R_\square \frac{L}{W} \tag{48}\]

The polysilicon resistor (Figure 42) uses the gate material (PC) as a resistive device. Since the gate poly is normally covered by silicide to lower its resistance, the silicide is suppressed with an OP shape; the intersection of OP with PC precisely defines the \(L\) and \(W\) of the resistor. Note that the existence of OP is a process option and might not be available in every technology. The gate polysilicon can be either \(p\)- or \(n\)-type; \(p\)-type poly resistors are often preferred, as they offer a lower temperature coefficient (thus the PC is marked with BP).

The resistance value of the polysilicon resistor is given by (\(R_\square\) is the sheet resistance in Ω/\(\square\))

Polysilicon Resistor

Figure 42: Layout of a polysilicon resistor: the silicide on the PC strip is blocked by the OP shape, whose intersection with PC defines the resistor body of length \(L\) and width \(W\); the BP marker selects \(p\)-type poly.

Layout of a polysilicon resistor: the silicide on the PC strip is blocked by the OP shape, whose intersection with PC defines the resistor body of length \(L\) and width \(W\); the BP marker selects \(p\)-type poly. The silicided ends are contacted with CA and M1.

4.3.3 Diffusion Resistor

Note that modern FinFET technologies might not support traditional planar polysilicon resistors, as the gate material is used to form the fins rather than a continuous sheet. In this case, often a metal resistor implemented in the back-end layers is used as an alternative.

Diffusion resistors (Figure 43) use source/drain diffusions or wells (with or without silicide) and are available in basically all silicon technologies, but they are usually inferior to polysilicon resistors: they have larger tolerances and a relatively high voltage coefficient, which can cause nonlinearity, and the nonlinear parasitic junction capacitance to the substrate can be critical as well. In older technology nodes (> 0.25 µm), the matching of diffusion resistors was better than that of poly resistors. One clear advantage of diffusion resistors is reduced self-heating, as the resistor body is embedded in the silicon substrate, whereas poly resistors are isolated from the substrate by SiO₂. So resistor with increased power dissipation can benefit from this property.

Diffusion Resistor

Figure 43: Layout of a diffusion (n-well) resistor: the resistive body is the NW strip, contacted at both ends by \(n^+\) diffusions (RX); the OP shape blocks the silicide over the body.

Layout of a diffusion (n-well) resistor: the resistive body is the NW strip, contacted at both ends by \(n^+\) diffusions (RX); the OP shape blocks the silicide over the body. The parasitic junction to the substrate makes this resistor nonlinear with the applied voltage.

Diffusion Resistor

Table 9: Resistor types available in IHP SG13

Type	\(R_\square\) (Ω/\(\square\))	Process tolerance (\(\pm 4 \sigma\))	Matching	Temp. coefficient
Silicided \(n^{++}\)-poly (rsil)	7	±12 %	0.6 %µm	0.3 %/K
Blocked \(p^+\)-poly (rppd)	260	±10 %	1.5 %µm	0.017 %/K
Blocked compensated poly (rhigh)	1360	±15 %	4.8 %µm	−0.23 %/K

The resistor types available in IHP SG13 are summarized in Table 9.

4.3.4 Capacitors

Linear capacitors can be implemented using the metal stack, either as vertical sandwich capacitors (parallel plates on adjacent metal layers) or as finger capacitors (exploiting the lateral coupling between interdigitated fingers on the same layers); both are shown in Figure 44. Depending on the design rules, the vertical or the lateral coupling capacitance might be more area-effective; such metal-oxide-metal (MOM) capacitors come for free in any technology. Due to the very tight lateral pitch is nm CMOS technologies, finger capacitors are often preferred for capacitor implementation (when a linear capacitor is required).

Capacitors

Figure 44: Metal-oxide-metal (MOM) capacitors: (a) vertical sandwich capacitor (cross section) using the plate capacitance between stacked metal layers, with alternating layers connected to the two terminals by via stacks; (b) finger capacitor (top view) using the lateral coupling capacitance between interdigitated fingers drawn in a single metal layer.

Capacitors

• The density of MOM capacitors scales with smaller design rules and the number of metal layers. The lower metal layers should be skipped if the parasitic capacitance to the substrate is a concern.
• The process may offer a specialized metal-insulator-metal (MIM) capacitor (density on the order of fF/µm²) using extra masks and processing steps, offering higher specific capacitance and low parasitics at extra cost.

A few additional considerations for capacitors:

Capacitors

• For high capacitance density, or where nonlinearity is not critical, the MOSFET gate capacitance can be used, as the gate oxide is tightly controlled in manufacturing.
• In IHP SG13, a MIM capacitor between Metal5 and TopMetal1 is available (ca. 1.5 fF/µm²); the MOM finger capacitor has ca. 0.3 fF/µm², so when using 4 metal layers the effective capacitance is comparable to the MIM capacitor.

4.3.5 Diodes

Diodes are formed by the available pn-junctions (\(n^+\) in substrate, \(p^+\) in n-well, n-well in substrate). They are intended mainly for reverse-biased operation, as the forward operation is usually not modeled accurately and should be avoided. Note that forward operation might inject charge into parasitic structures and cause latch-up (see Section 9.2)! Applications of reverse-biased diodes include ESD protection structures, antenna diodes, and varactors.

4.3.6 Bipolar Junction Transistors

High-performance BJTs are available in bipolar and BiCMOS technologies, but at increased wafer cost compared to pure CMOS. In standard CMOS, a parasitic vertical substrate PNP can be implemented (Figure 45): the \(p^+\) diffusion in the n-well forms the emitter, the n-well the base, and the common \(p\)-substrate the collector. The performance is limited (\(\beta \approx 1 \ldots 10\)), and the collector is tied to the substrate potential. Such a structure is mainly used in bandgap reference circuits where collector and base are shorted to \(V_\mathrm{SS}\) (ground), and the foundry usually supplies a fixed layout template that shall not be modified.

Bipolar Junction Transistors

Figure 45: Cross section of the vertical substrate PNP available in any CMOS technology: the \(p^+\) diffusion in the n-well is the emitter, the n-well is the base, and the common \(p\)-substrate is the collector (contacted at the surface and tied to \(V_\mathrm{SS}\)).

4.4 Design Rules

Design Rules

• The design rules are provided as a specification document and as a run set for layout verification tools (e.g., KLayout, Magic, Cadence Pegasus, or Siemens Calibre).
• The rules are either given in relative dimensions (“lambda rules”) for easy scaling, or in absolute dimensions (“micron rules”).
• Modern CMOS technologies typically involve several hundred to thousands of layout design rules.

The design rules (DRs) are the interface between the mask designer (layout engineer) and the foundry. Complying with the layout design rules ensures manufacturability with a high yield:

Design Rules

• Consider the relatively large spacing rule between RX and NW: it pays off to group PMOS and NMOS transistors together, respectively!

The four basic geometric rule types—minimum width, minimum spacing, minimum enclosure, and minimum extension—are illustrated in Figure 46.

Design Rules

Figure 46: The four basic geometric design-rule types: (a) minimum width of a shape, (b) minimum spacing between shapes, (c) minimum enclosure of one shape by another (e.g., RX in NW), and (d) minimum extension of one shape beyond another (e.g., the poly endcap over RX).

4.4.1 Density Rules

Density rules require a minimum and a maximum layer density within a specified area; this is needed to avoid over-polishing during CMP and to achieve uniform etch rates. For example, M1 might require 30 % minimum and 70 % maximum fill in any 1 mm × 1 mm window. For digital chips, density rules are satisfied automatically by fill programs. For analog chips, layout engineers have to add dummy structures manually (effort!) or with a fill program after the layout is finished; note that fill structures can cause asymmetries or reduced quality factor in inductors. Metal fill can also be put to good use as a ground plane.

4.4.2 Antenna Rules

If a metal interconnect with a large area is tied to the small gate of a MOSFET, the metal area acts as an “antenna” during plasma etching: it collects ions and can rise to a high potential, and the gate oxide may break down! The remedies, shown in Figure 47, are either a discontinuity in the charge-collecting metal (routing briefly through a higher metal layer, which is patterned only after the lower layer has been etched) or an antenna diode connected to the gate node (the processing is done at high temperatures, where the diode is quite conductive in either polarity, harmlessly draining the collected charge).

Antenna Rules

Figure 47: The antenna effect and its fixes (cross sections): (a) a long M1 wire connected to a gate collects charge during plasma etching and can destroy the gate oxide; (b) breaking the M1 wire and bridging with M2 limits the charge collected while M1 is etched; (c) an antenna diode drains the collected charge harmlessly into the substrate.

4.5 Analog Layout Techniques

The complete layout rules of the open-source IHP SG13 PDK can be found in the SG13G2 layout rules document and serve as a practical example of a production DRC rule set.

4.5.1 Multi-Finger Transistors

Analog circuits, unlike digital ICs, do not primarily aim to maximize density, but demand the minimization of effects such as crosstalk, mismatch, and noise. Useful techniques are multi-finger transistors, matching and symmetry, and careful floor planning; further treatments of analog layout can be found in (Razavi 2017; Allen and Holberg 2012), and an exemplary analog IC design employing these techniques is described in (Schmickl et al. 2020).

A transistor with a large \(W\) should be split into multiple parallel devices (“fingers”) to make the layout structure compact, as shown in Figure 48. This splitting also reduces the gate resistance (see Equation 32; for RF, keep the resistance of each gate finger below \(1/g_\mathrm{m}\)) and can lower the junction capacitance at the drain or source, since neighboring fingers share their diffusion regions.

Multi-Finger Transistors

Figure 48: Multi-finger transistor: instead of a single device with a very large width (left), the transistor is split into four parallel fingers (right), which share their source/drain diffusions.

Multi-finger transistor: instead of a single device with a very large width (left), the transistor is split into four parallel fingers (right), which share their source/drain diffusions. The layout gets compact, the gate resistance drops, and the junction capacitance is reduced.

Multi-Finger Transistors

Figure 49: Merged diffusion in a series connection of two equally sized MOSFETs (e.g., a cascode): the drain of \(M_1\) and the source of \(M_2\) share the same diffusion region, which can be kept minimal because it carries no contacts—saving area and junction capacitance.

The layout of a cascode circuit (or any series connection of MOSFETs, e.g., in NAND/NOR gates) can be simplified if the stacked devices have equal widths: the drain of the bottom device and the source of the top device can then share the same diffusion region, which is small because it needs no contacts, as shown in Figure 49.

4.5.2 Matching

• The devices are constructed from identical unit devices: a MOSFET with width \(4W\) matches a transistor with width \(2W\) only if both are constructed from unit transistors of equal width (and equal \(L\)—remember that \(V_\mathrm{th}= f(L)\) due to SCE/RSCE)!
• The devices are oriented in the same direction, and the current flow in all matched devices has the same direction—avoid mirroring or “snaking”!

Asymmetries lead to mismatch, which introduces input-referred offsets and limits the minimum processable signal level; common-mode and power-supply rejection are degraded as well. Good matching of integrated devices can only be achieved if the following conditions are met:

Matching

• The devices are surrounded by similar structures; to achieve this for edge devices, spend dummy elements (see Figure 50).
• To combat process gradients, place the matched devices on the symmetry line of the gradient (if known), or use common-centroid arrangements (see Figure 52).
• For ac symmetry, consider the wiring of \(R\) and \(C\), and make the wiring parasitics as symmetrical as possible.

Matching

• Consider secondary effects: gate shadowing (implant variation due to topographical differences and tilted implant angle), mechanical stress from shallow-trench isolation, and non-uniform doping due to the well-proximity effect (dopants scattering off the well-mask edges cause doping variations, especially impacting PMOS).

Matching

Figure 50: Dummy fingers for matching: the two matched transistors \(M_1\) and \(M_2\) are surrounded by unused dummy gate fingers, so that every active finger sees identical neighbors; this equalizes etch loading and STI stress.

Dummy fingers for matching: the two matched transistors \(M_1\) and \(M_2\) are surrounded by unused dummy gate fingers, so that every active finger sees identical neighbors; this equalizes etch loading and STI stress. The dummy gates and the outer dummy diffusions are tied to ground so that they stay off and well defined. \(M_1\) and \(M_2\) share the center source diffusion, i.e., all source regions form one common node, which makes this arrangement directly usable as a differential pair or a current mirror.

Matching

Figure 51: Array of four matched unit resistors \(R_1 \ldots R_4\): all strips have identical width and length, the same orientation, and the same pitch, and the silicide block OP runs across the whole array so that every resistor body sees the same edge.

The same reasoning applies to passive devices. Figure 51 shows an array of four matched unit resistors: identical width and length, identical orientation, and a constant pitch, so that \(R_1\) and \(R_4\) at the edges see the same surroundings as \(R_2\) and \(R_3\) in the middle. Note that the dummy strips are not left floating, but are shorted and tied to ground to keep them at a defined potential.

Array of four matched unit resistors \(R_1 \ldots R_4\): all strips have identical width and length, the same orientation, and the same pitch, and the silicide block OP runs across the whole array so that every resistor body sees the same edge. A dummy strip at each end gives the outer resistors the same neighborhood as the inner ones. The dummies are shorted by metal and tied to ground, so they sit at a defined potential instead of floating.

Matching

Figure 52: Common-centroid arrangements of two matched devices A and B, each split into two halves: (a) cross-coupled 2×2 arrangement and (b) linear ABBA arrangement.

Gradients across a die can be caused by doping and film-thickness variations (well approximated by a linear gradient for devices in proximity), by temperature gradients originating from areas with large power dissipation, and by mechanical stress from packaging or metallization (avoid low-level metal routing over sensitive devices). A common-centroid arrangement cancels linear gradients to first order, as shown in Figure 52: each component is decomposed into two or more parts that are placed diagonally opposite each other, so that all component centroids coincide.

Common-centroid arrangements of two matched devices A and B, each split into two halves: (a) cross-coupled 2×2 arrangement and (b) linear ABBA arrangement. In both cases, the centroids of A and B coincide, so a linear process gradient (illustrated by the color wedge) affects both devices equally.

Matching

Figure 53: Precisely matched capacitor pair with \(C_1 = 8 C_2\), built from identical unit capacitors: the single \(C_2\) unit sits at the common centroid of the eight \(C_1\) units, and a ring of grounded dummy capacitors (D) ensures that every active unit sees identical surroundings.

The same principle applies to capacitors: Figure 53 shows a matched capacitor pair with a ratio of \(C_1 = 8 C_2\), realized from identical unit capacitors with a common centroid and surrounded by dummy capacitors. If \(C_1\) and \(C_2\) are used, e.g., in a switched-capacitor amplifier, the voltage gain can be precisely set to \(A_\mathrm{v} = C_1 / C_2 = 8\).

4.5.3 Floor Planning

• Locations of pins and interfaces; distribution of \(V_\mathrm{DD}\) and \(V_\mathrm{SS}\) pins; isolation of sensitive I/O signals.
• Cell sizes and aspect ratios (allowing an area-efficient placement of the macros).
• Isolation between different circuit blocks (e.g., keep sensitive analog blocks away from noisy digital blocks).
• Power and clock distribution; wiring channels for signal buses.
• The package type used (wire-bond or flip-chip).

Floor planning is an important task when constructing the overall IC layout. Things to consider are:

A common mistake: a great job laying out lots of cells, then running out of time, resulting in a big mess when placing and connecting them—start with a top-down plan!

4.6 Additional Layout and Mask Structures

Additional Layout and Mask Structures

• Seal ring: The seal ring runs along the circumference of the chip and seals the singulated die against moisture and other contamination. It also acts as a crack-stop, protecting the inner die from cracks formed while sawing the wafer into individual dice. Since the seal ring forms a closed metal loop around the chip, crosstalk considerations may suggest connecting it to a dedicated pin.

In addition to the final chip layout, further structures are placed on the masks (usually by the wafer fab):

Additional Layout and Mask Structures

• Scribe line (kerf): This is where the chip is cut with a diamond saw or a laser.
• Alignment marks: Used to align the different masks during processing.
• Critical-dimension structures: Measured after processing to verify proper polysilicon or metal etching, enabling closed-loop process control.
• Vernier structures (“Nonius”): Closely spaced parallel lines on two different layers that allow judging the inter-layer alignment.

Additional Layout and Mask Structures

• Test structures: Chains of contacts and vias, as well as test transistors, are used to evaluate contact resistance, transistor parameters, and other important process parameters. They are usually placed in the scribe lines or on dedicated process control monitor (PCM) test chips; the PCM measurement reports can often be obtained from the foundry.

4.7 Layout Checks

Layout Checks

• DRC (design rule check): a program/run set that automatically checks the layout data for compliance with the design rules of the wafer fab. All flagged errors must be corrected; otherwise, manufacturing issues can occur.
• LVS (layout versus schematic): a netlist extracted from the layout data is compared against the schematic netlist, checking connectivity of signals and power as well as device sizes (\(W\) and \(L\) of transistors, dimensions of \(R\) and \(C\)). Usually, all flagged errors must be corrected.

Three automated checks safeguard the layout before tapeout:

Layout Checks

• ERC (electrical rule check): additional checks not covered by DRC or LVS, such as floating MOSFET gates, floating wells, or antenna rules. Sometimes common mistakes (e.g., high-resistance connections) are covered in the ERC run set and checked automatically.

4.8 Layout Extraction

Layout Extraction

• Wiring adds delays (\(R\), \(L\), \(C\)) and coupling (\(k\), \(C\)) to the circuits.
• Layout-dependent effects (LDE), like well proximity, can only be modeled with information about the actual layout of the devices and their surroundings.
• Substrate effects (like crosstalk) can only be extracted from the actual placement.

The layout implementation has a large effect on the performance of the final circuit:

Considering layout effects in simulation is paramount and usually requires iteration between circuit design and layout: circuit design and simulation → layout creation → parasitic extraction → re-simulation → circuit and/or layout refinement → repeat. In the digital flow, wiring delays extracted from the layout are added to the gate-level netlist for timing analysis, and voltage drops in the power network (\(V_\mathrm{DD}\)/\(V_\mathrm{SS}\) droop and ripple) are extracted and considered as additional timing derating. For analog and high-performance circuits, simulation including layout parasitics is mandatory to guarantee the performance and functionality of the fabricated circuit!

Different levels of extraction realism trade off accuracy against simulation speed:

Layout Extraction

• C-decoupled: The parasitic capacitance of each node’s wiring is added as a lumped capacitor to ground. There is almost no impact on simulation speed (no new nodes are introduced), but no crosstalk between nodes is captured. This extraction can be used on fairly large circuits to add a first level of realism.

Layout Extraction

• C-coupled: Parasitic capacitances to the substrate and between nodes are added; capacitive crosstalk is modeled, but no inductive effects. Moderate impact on simulation speed (more elements in the circuit matrix).
• RC-extracted: Parasitic \(R\) and \(C\) of the wiring are extracted and added to the netlist, yielding a realistic model of performance and crosstalk without inductive effects. This has a large impact on simulation speed, as many new nodes are introduced; this mode should be used for circuit blocks of moderate complexity.

Layout Extraction

• RLCK-extracted: Parasitic \(R\), \(C\), \(L\), and \(k\) of the wiring are extracted, resulting in a very accurate simulation including the main crosstalk effects—but the circuit network gets much larger, impacting simulation time and convergence.
• EM simulation: Highest accuracy; the resulting \(S\)-parameters are either used directly in frequency-domain simulations or transformed into equivalent lumped-element circuits. Huge simulation-time impact, but valid to very high frequencies (> 100 GHz); usually only suitable for individual circuit blocks.

Layout Extraction

Parasitic Extraction with KLayout-PEX

Our open-source parasitic extraction tool KLayout-PEX (invoked as kpex) implements several of these extraction levels for KLayout, using different engines (an analytical 2.5D engine, a wrapper around MAGIC, and the FasterCap 3D field solver) that trade off speed against accuracy. Supported PDKs include IHP SG13G2 and SkyWater sky130A. Further information can be found in the online documentation.

References

Allen, Phillip E., and Douglas R. Holberg. 2012. CMOS Analog Circuit Design. 3rd ed. Oxford University Press.

Razavi, Behzad. 2017. Design of Analog CMOS Integrated Circuits. 2nd ed. McGraw-Hill Education.

Schmickl, Stefan, Tim Schumacher, Patrick Fath, Thomas Faseth, and Harald Pretl. 2020. “A 350-nW Low-Noise Amplifier with Reduced Flicker-Noise for Bio-Signal Acquisition.” Austrochip Workshop on Microelectronics, 9–12. https://doi.org/10.1109/Austrochip51129.2020.9232981.

References