Robust Design

Design of Complex Integrated Circuits

10 Robust Design

Robust Design

1. Go for robust circuits and layouts that are insensitive to PVT (process, voltage, temperature) influences.
2. Keep in mind that fabrication variations are normal; use the foundry-supplied corner models to check the design against parameter excursions and component mismatch.
3. PCB, IC package, and on-chip wiring all add \(R\), \(L\), \(C\), \(k\) parasitics—model them properly and include them in the circuit simulation.

Better than debugging a failing IC is avoiding design issues up front! A good overall strategy for IC design is:

Robust Design

4. During all phases of design and layout, think about what could go wrong, and build in remedies for debug and fix (layout locations where a cut or short can easily be made by FIB or a metal redesign, spare elements, programmability).

This chapter follows these four points, and closes with structured methods and tools for the case where, despite all precautions, first silicon does not behave as expected.

10.1 Robust Circuits and Layouts

Robust Circuits and Layouts

• Define gains by resistor ratios or capacitor ratios.
• Set currents by the ratio of a current mirror.
• Time as a parameter can be handled efficiently and accurately (crystal-referenced); if possible, base the circuit principle on timing.

Absolute parameters of IC components (MOSFETs, \(R\), \(C\)) vary a lot in production (\(V_\mathrm{th}\) by \(\pm 100\,\text{mV}\), other parameters by ±10 to ±30 %), but ratios can be produced very accurately. Therefore:

A few further circuit-level habits make a design tolerant against the remaining variations:

Robust Circuits and Layouts

• Use negative feedback: the closed-loop gain of an amplifier is set by the feedback network (a ratio again), and is largely independent of the poorly controlled open-loop gain.
• Derive bias currents from a well-defined reference (e.g., a bandgap voltage across a resistor, or a constant-\(g_\mathrm{m}\) bias) instead of a plain supply-referenced resistor, so the circuit performance tracks with process and temperature in a controlled way.

Robust Circuits and Layouts

• Prefer differential signal paths: supply noise, substrate coupling, and even-order distortion appear as common-mode disturbances and are rejected to first order.
• Where the achievable accuracy is not sufficient, plan for calibration or trimming (see Section 6.5) instead of over-designing the circuit.

Mismatch of IC components is inherent to wafer production, but can be made worse by bad layout or non-matched sizing: matching is best when devices are constructed from unit elements, with matched size, orientation, wiring, and current-flow direction (see Section 4.5). The random part of the mismatch between two identical, closely spaced devices scales with their area, as described by the Pelgrom model (Pelgrom et al. 1989):

Robust Circuits and Layouts

\[ \sigma(\Delta V_\mathrm{th}) = \frac{A_{V_\mathrm{th}}}{\sqrt{W L}} \tag{65}\]

Mismatch versus Area

• Matching is best with unit elements: same size, orientation, wiring, and current-flow direction
• \(A_{V_\mathrm{th}}\) is supplied by the foundry (a few \(\text{mV}\cdot\mu\text{m}\))
• Example: \(A_{V_\mathrm{th}} = 5\,\text{mV}\cdot\mu\text{m}\), \(W L = 1\,\mu\text{m}^2\) \(\rightarrow\) \(\sigma(\Delta V_\mathrm{th}) = 5\,\text{mV}\)
• Halving the mismatch costs 4× area (and capacitance)
• Fundamental trade-off between accuracy, area, and speed

The matching coefficient \(A_{V_\mathrm{th}}\) is supplied by the foundry and is in the range of a few \(\text{mV}\cdot\mu\text{m}\) for current CMOS technologies. With \(A_{V_\mathrm{th}} = 5\,\text{mV}\cdot\mu\text{m}\), a transistor pair with \(W L = 1\,\mu\text{m}^2\) has \(\sigma(\Delta V_\mathrm{th}) = 5\,\text{mV}\); halving the mismatch costs four times the area (and capacitance). Equation 65 is thus a fundamental trade-off between accuracy, area, and speed, which is analyzed in detail in (Kinget 2005); practical layout measures for matching and robustness are collected in (Hastings 2006).

Production and Lifetime

• Anticipate the production flow:
  • masks can be offset relative to each other, gradients across the wafer happen
  • single defects must not cause failure (use multiple vias!)
  • layout is post-processed (filling, cheesing, dummy structures)
• A working circuit has to keep working for years—wear-out mechanisms:
  • electromigration in wires and vias (respect the PDK current-density limits)
  • gate-oxide breakdown (TDDB)
  • \(V_\mathrm{th}\) drift by HCI and NBTI/PBTI
• Keep all terminal voltages within the rated limits in all operating states (power-up, power-down, block disabled)

Keep the production flow in mind to anticipate good layout practices: masks can be offset relative to each other, gradients across the wafer will happen, single defects should not cause circuit failure (use multiple vias!), and the layout will be post-processed for manufacturability (filling, cheesing, dummy structures).

Robustness also has a lifetime dimension: a circuit that works at time zero has to keep working over years of operation (see Section 3.10). Relevant wear-out mechanisms are electromigration in wires and vias (respect the current-density limits of the PDK, especially for supply lines and output drivers), gate-oxide breakdown (TDDB), and \(V_\mathrm{th}\) drift by hot-carrier injection (HCI) and bias-temperature instability (NBTI/PBTI). Hence, keep all device terminal voltages within the rated limits of the respective device type in all operating states—including power-up, power-down, and when a block is disabled.

10.2 Corner Models

Corner Models

• Smallest/largest \(R\), smallest/largest \(C\), etc.
• Slow/fast PMOS and slow/fast NMOS, usually grouped into the corner sets SS, SF, TT, FS, FF (first letter NMOS, second letter PMOS).

To check the influence of production parameter variations, the foundries supply corner models. Model files are provided for the nominal corner (TT), reflecting the target values of production, and for the expected parameter extremes (usually \(3\sigma\) to \(5\sigma\)):

All available corner files should be simulated to check the circuit performance against production spread; in addition, temperature and supply voltage (defined early in the IC specification) have to be varied. This results in many simulation runs, requiring automated simulation control and data post-processing. Which combination is the worst case depends on the circuit and on the parameter under test:

Corner Models

• For digital timing, the slow corner (SS, lowest supply, highest temperature) usually limits the maximum clock frequency (setup time), whereas the fast corner (FF, highest supply, lowest temperature) is critical for hold-time violations and leakage. In advanced low-voltage nodes, temperature inversion can make low temperature the slowest condition.
• The skewed corners SF and FS are critical for circuits relying on a balance between NMOS and PMOS, such as the switching threshold of an inverter, ratioed logic, or SRAM cells.

Corner Models

• Analog circuits can have their worst case in any corner, so no corner should be skipped.

Monte-Carlo Mismatch

• Corners: fully correlated global process shift
• Monte-Carlo: random local mismatch, device parameters varied in every run
• Result is a distribution of the circuit performance (e.g., comparator offset) \(\rightarrow\) mean and \(\sigma\)
• Specs need a margin of several \(\sigma\) \(\rightarrow\) at least a few hundred runs
• Critical blocks: Monte-Carlo mismatch runs on top of the process corners
• Do not stack all worst cases at their extremes \(\rightarrow\) over-design; the spec states which conditions apply simultaneously

Component mismatch (as opposed to global process shift) is covered by Monte-Carlo models, in which device parameters are randomly varied for each simulation run according to their statistical distribution. The result is a distribution of the circuit performance (e.g., the input offset of a comparator), from which mean and standard deviation are estimated. Since a specification is usually required to be met with a margin of several \(\sigma\) (see Section 6.6), and the estimate of \(\sigma\) itself is uncertain for few samples, a meaningful Monte-Carlo analysis needs at least a few hundred runs. Corner models describe the (fully correlated) global process shift, while Monte-Carlo mismatch describes random local variations; for critical blocks, both have to be combined, i.e., Monte-Carlo mismatch runs are performed on top of the process corners.

Note that stacking all worst cases at their extremes (slowest process, lowest supply, highest temperature, \(3\sigma\) mismatch, maximum parasitics) quickly leads to an over-designed circuit wasting power and area. A good specification states which conditions have to be met simultaneously.

10.3 Include the Parasitics

Include the Parasitics

• For first investigations, hand-calculated values are a good starting point (see Section 5.5).
• For on-chip circuits, parasitic extraction (PEX) of the layout blocks is mandatory (see Section 4.8).
• For IC packages, first-order lumped models can be refined by calculated EM models (e.g., \(S\)-parameters).
• The same holds for PCB effects; if no simulation model is available, approximate the important effects by calculating \(R\), \(L\), \(C\), \(k\) from the geometry.

Supply, Ground, and Substrate

• Easily overlooked: parasitics outside the signal path
• Bond-wire inductance \(\rightarrow\) supply and ground bounce (\(L\,di/dt\))
• Resistive on-chip supply lines \(\rightarrow\) static and dynamic IR drop
• Disturbances couple into every block on the same supply, and via the resistive substrate
• Remedies: on-chip decoupling, separate supplies for noisy and sensitive blocks, parallel bond wires, guard rings
• No model available? Add a pessimistic estimate—an ideal supply and a perfect ground hide the problems seen in the lab

All circuit wiring adds \(R\), \(L\), \(C\), \(k\) parasitics: PCB traces and cables, package parasitics like bond wires, and on-chip interconnect. Having a unified simulation setup capturing all these impairments is a must, as unwanted effects like crosstalk or degraded performance can often be root-caused to them:

Parasitics that are easily overlooked, because they are not part of the signal path, are those of the supply and ground network: a current step through the bond-wire inductance causes supply and ground bounce (\(L\,di/dt\)), and resistive on-chip supply lines cause static and dynamic IR drop. These disturbances couple into every block sharing the same supply, and also into the substrate, which connects all devices on the die through a resistive network (Afzali-Kusha et al. 2006). Common remedies are on-chip decoupling capacitors, separate supply and ground pins for noisy (digital, output drivers) and sensitive (analog, RF) blocks, multiple parallel bond wires, and guard rings around sensitive circuits. When no model of such an effect exists, add a pessimistic estimate to the testbench—an ideal supply and a perfect ground hide exactly the problems that show up in the lab.

10.4 Failure-Mode Thinking

Failure-Mode Thinking

• If feedback-loop stability is a concern, make the compensation components (feedback \(R\) and \(C\)) programmable (using register bits and transmission gates to switch components in and out).
• If there is a critical bias point in the circuit, make it observable (connect it to a test pad via a T-gate) or programmable (adapt voltages or currents by programming, metal redesign, or FIB).

During the complete design phase, an important habit is “failure-mode thinking,” i.e., asking “what could go wrong?” (paranoia is a good trait in IC design). By anticipating potential issues, remedies and debug hooks can be built into the design. Some examples:

Failure-Mode Thinking

• For complex logic functions, add spare logic gates nearby (a few NAND gates, inverters, latches, and delay elements) to allow fixing overlooked logic bugs in a metal-only redesign.
• If circuit sizing is uncertain, place spare elements (\(R\), \(C\), MOSFETs, logic gates) that can be connected in a metal redesign, or by FIB for a handful of repaired samples; often, dummy elements can double in this role.

Failure-Mode Thinking

• If the risk is very high, implement multiple design variants of a circuit on one tape-out, so the best variant (based on measurements) can be selected and refined for the next tape-out.
• Route internal nodes that are hard to measure (bias voltages, reference clocks, the output of a sub-block) to an analog test bus or a test multiplexer, and provide bypass and loop-back modes, so each block of a signal chain can be characterized in isolation.

Failure-Mode Thinking

• Make sure the circuit always reaches its intended operating point: self-biased circuits like bandgap references and current references can have a second, degenerate stable state (all currents zero) and need a start-up circuit. Power-up and power-down sequences, undefined reset states, and floating inputs of disabled blocks deserve dedicated simulations.

Failure Mode and Effects Analysis

• Formalized failure-mode thinking for larger projects
• Systematically list potential failure modes
• Rank them by severity, likelihood, and detectability
• Mandatory, e.g., for automotive ICs

For larger projects, this informal habit can be formalized as a failure mode and effects analysis (FMEA), in which potential failure modes are systematically listed and ranked by severity, likelihood, and detectability; FMEA is mandatory, e.g., for automotive ICs.

10.5 Debugging of ICs

Debugging of ICs

1. Reproduce the failure reliably and document the conditions (sample, supply, temperature, input signals); check whether all samples fail or only some (a design issue versus a production defect).
2. Isolate the failing block, e.g., using the test modes, bypass paths, and observable nodes built in during the design phase.
3. Collect potential causes and form a hypothesis (the methods below help here).

If first silicon fails, the pressure to find a quick fix is high, and the temptation is to change several things at once based on a first guess. A disciplined procedure is usually faster:

Debugging of ICs

4. Confirm the hypothesis by reproducing the failure in simulation, and by predicting a further observation that is then checked in the lab.
5. Only then implement and verify the fix—first in simulation, then on silicon (e.g., by a FIB repair of a few samples) before the redesign is taped out.

10.5.1 The Fishbone Diagram

• People: anyone involved in the process.
• Methods: policies, procedures, rules, and regulations.
• Machines: computers, tools, and equipment required to accomplish the job.
• Materials: raw materials, parts, and consumables used to produce the final product.
• Measurements: data generated from the process, used to evaluate its quality.
• Environment: the conditions—location, time, temperature, culture—in which the process operates.

During the root-cause analysis of a failure, a structured method of investigation helps; the fishbone (Ishikawa) diagram shown in Figure 89 visualizes the cause-and-effect investigation (Ishikawa 1976). In a tree-like structure, the potential causes leading to an effect are organized, and details (branches) are added as debugging or brainstorming progresses. Causes are usually grouped into categories:

The Fishbone Diagram

Figure 89: Fishbone (Ishikawa) diagram for structured root-cause analysis: the effect (the observed problem) forms the head, the main bones are the cause categories, and detailed causes are added as smaller branches during the investigation.

10.5.2 The “5-Why” Method

1. “Why did the robot stop?” → The circuit overloaded, causing a fuse to blow.
2. “Why did the circuit overload?” → There was insufficient lubrication on the bearings, so they locked up.
3. “Why was there insufficient lubrication?” → The oil pump is not circulating enough oil.
4. “Why is the pump not circulating enough oil?” → The pump intake is clogged with metal shavings.
5. “Why is the intake clogged?” → Because there is no filter on the pump.

A helpful strategy to identify causes is the “5-why” method: ask “Why…?” five times in succession (five is just a rough number—more or less, depending on complexity); the method originates from the Toyota production system (Ohno 1988). An example:

This may sound simple, but in a complex setting (time pressure, pressure from management or customers), analyzing an issue with simple, structured methods is an effective way to make progress.

10.5.3 Focused Ion Beam (FIB)

• A FIB machine uses ions (e.g., Ga) to remove material from a sample by sputtering/milling, with a resolution down to about 10 nm.
• Using a reactive gas inside the vacuum chamber, FIB-assisted CVD can deposit structured layers of, e.g., tungsten, forming new electrical connections.
• Since the deposited layers are very thin, creating low-ohmic connections is difficult—so a cut is preferable to a new connection where possible.

Preparing for FIB

• FIB access is easiest on the top metal layers
• Route candidate nets (at least a short section) on top metal
  • away from dense wiring
  • not covered by metal fill
• Flip-chip or dense metal stacks: backside FIB of the thinned die possible, but considerably more difficult

The focused ion beam (FIB) is an extremely helpful technique to modify on-chip circuitry, by cutting connections and/or creating new on-chip connections (it can also create probe pads for micro-probing) (Giannuzzi and Stevie 2005):

FIB access is easiest on the top metal layers; nets that are candidates for a FIB modification should therefore be routed (at least for a short section) on top metal, away from dense wiring, and not be covered by metal fill. For flip-chip packages or dense metal stacks, FIB modifications from the backside of the thinned die are possible, but considerably more difficult.

10.5.4 Failure Analysis

• Micro-probing: fine needles (or FIB-created probe pads) contact internal nodes to measure voltages and waveforms directly.
• Hot-spot detection: shorts, leaky junctions, and latched structures dissipate power locally, which can be localized by thermal imaging (e.g., lock-in thermography) or by liquid-crystal coatings changing their appearance with temperature.
• Photon emission microscopy: forward-biased junctions, MOSFETs in saturation, and oxide breakdown emit weak light (mostly in the infrared), which can be detected, also through the backside of the die.

Beyond electrical measurements at the pins, several physical failure-analysis techniques help to locate a fault on the die (a comprehensive overview is given in (Gandhi 2019)):

Failure Analysis

• X-ray inspection and acoustic microscopy reveal package defects like broken bond wires, voids, or delamination non-destructively; afterwards, the die can be exposed by decapsulation and inspected optically or in a scanning electron microscope (SEM).

References

Afzali-Kusha, Ali, Makoto Nagata, Nishath K. Verghese, and David J. Allstot. 2006. “Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation.” Proceedings of the IEEE 94 (12): 2109–38. https://doi.org/10.1109/JPROC.2006.886029.

Gandhi, Tejinder, ed. 2019. Microelectronics Failure Analysis Desk Reference. ASM International.

Giannuzzi, Lucille A., and Fred A. Stevie, eds. 2005. Introduction to Focused Ion Beams: Instrumentation, Theory, Techniques and Practice. Springer. https://doi.org/10.1007/b101190.

Hastings, Alan. 2006. The Art of Analog Layout. 2nd ed. Prentice Hall.

Ishikawa, Kaoru. 1976. Guide to Quality Control. Asian Productivity Organization.

Kinget, Peter R. 2005. “Device Mismatch and Tradeoffs in the Design of Analog Circuits.” IEEE Journal of Solid-State Circuits 40 (6): 1212–24. https://doi.org/10.1109/JSSC.2005.848021.

Ohno, Taiichi. 1988. Toyota Production System: Beyond Large-Scale Production. Productivity Press.

Pelgrom, Marcel J. M., Aad C. J. Duinmaijer, and Anton P. G. Welbers. 1989. “Matching Properties of MOS Transistors.” IEEE Journal of Solid-State Circuits 24 (5): 1433–39. https://doi.org/10.1109/JSSC.1989.572629.

References