Testing

Design of Complex Integrated Circuits

6 Testing

6.1 Post-Silicon Production Flow

Integrated circuits must be tested for functionality and specification compliance before they are shipped. Defects introduced during manufacturing, as well as parameter variations, are unavoidable—not every IC on a wafer is a good device (the yield is below 100 %). Typical defect causes are doping errors and fluctuations, under- or over-etching, misalignment of layers, and contamination by particles. A comprehensive treatment of IC test is given in (Wang et al. 2006); the related field of hardware security and trust is covered in (Bhunia and Tehranipoor 2018).

Post-Silicon Production Flow

1. Wafer test (optional): bad dice are inked or recorded in the automatic test equipment (ATE) to avoid wasting packages on them. The cost of packaging a bad die has to be weighed against the cost of the wafer test.
2. Wafer dicing: the wafer is cut into separate chips, and bad chips are discarded.
3. Packaging.
4. Final test: ensures that no parts damaged during dicing or packaging are shipped; some parameters might only be testable on the packaged device.

The production flow after wafer manufacturing consists of the following steps:

The ATE is typically used in two distinct modes:

Post-Silicon Production Flow

• Prototype/characterization testing is very extensive: it looks for worst-case behavior across conditions, establishes guard bands (margins for temperature and measurement uncertainty), is statistically based across hundreds or thousands of engineering samples, and test time is not the main concern.
• Production testing is very time-critical: the tester is expensive, so minimum test time matters; the tests are based on the worst-case conditions established during characterization, and each IC is tested individually.

6.2 Test Equipment

Test Equipment

1. The workstation: the user computer of the test engineer, used for debugging and day-to-day operation of the tester.
2. The mainframe: houses the power supplies and measurement instruments and contains the tester computer (including DSP hardware for fast signal analysis).
3. The test head: contains the most sensitive measurement electronics, and carries the device interface board (DIB) connecting to the device under test (DUT).

Mixed-signal IC test equipment (manufacturers include Teradyne, Advantest, Cohu, and National Instruments) consists of the parts shown in Figure 59:

Test Equipment

Figure 59: Structure of a mixed-signal automatic test equipment (ATE): the workstation controls the mainframe (power supplies, instruments, tester computer with DSP), which connects to the test head carrying the sensitive measurement frontends and the device interface board (DIB) with the DUT socket; a handler feeds the devices.

6.3 Mixed-Signal Testing Challenges

The DIB is a custom-designed PCB that hosts the package socket (for testing packaged ICs) or connects to the probe card (for wafer testing). It also contains interface circuits that cannot be handled by the tester hardware resources (e.g., special components required by the DUT). Contact to the packaged DUT is made with spring-loaded “pogo pins” in the socket. For wafer probing, different probe-card types are used: cantilever probe cards (needles coming in at an angle), vertical (“buckling-beam” or “cobra”) probe cards, and membrane probe cards for high pin counts and fine pitches.

Handlers (robotic pick-and-place or gravity-fed) insert the DUT into the test socket on the DIB. After the test, the ICs are sorted into bins (good = pass, bad = fail, possibly multiple pass grades). The handler can also provide a temperature-controlled environment for hot/cold testing in addition to room-temperature testing (the latter is preferred for cost reasons).

Mixed-Signal Testing Challenges

• Time is money: A tester plus handler can cost several million dollars, and one second of test time costs 3 to 5 cents. The test program needs a certain time (up to minutes) to cover all relevant functional blocks and critical parameters. Multi-site testing (testing 2/4/8 devices in parallel) reduces the effective test time per device.
• The test socket introduces parasitics (\(R\), \(L\), \(C\)) which impact performance and make precision measurements difficult.

Mixed-Signal Testing Challenges

• Accuracy is limited by interference, calibration, and measurement time.
• Repeatability & reproducibility (R&R) are required to obtain the same test results across different testers, DIBs, and test sites.

The classification of measurement errors is summarized in Figure 60: accuracy relates the measurement to the true value (via instrument traceability to standards), while precision splits into repeatability and reproducibility, illustrated in Figure 61.

Mixed-Signal Testing Challenges

Figure 60: Classification of measurement errors: accuracy is ensured by instrument traceability to standards, while precision splits into repeatability (same person, machine, and setup) and reproducibility (different person, machine, or setup).

Mixed-Signal Testing Challenges

Figure 61: Repeatability versus reproducibility: (a) repeatability is the spread of a single measurement setup; (b) reproducibility is the difference between the mean values obtained by different operators, machines, or setups.

Repeatability is the dispersion of measurements when a quantity is measured several times under the same conditions: same measuring instrument, same parts, same operator, within a short time period. It represents the inherent variation of the measurement system—note that measurements may show good repeatability without being accurate! Reproducibility is the variation between the mean measurements on the same parts when one condition is changed per trial: a different operator, a different instrument, or a different setup.

6.4 The Test Plan

The Test Plan

• Device background information (in addition to the datasheet).
• Special test requirements.
• An explanation of the purpose of each test.
• Assumptions made for particular tests, and why.
• A hardware setup diagram for each test.
• Identification of critical test parameters: not all parameters from the datasheet need to be (or can be) tested in production, due to test time or measurement error; such parameters are guaranteed by design and marked accordingly in the datasheet.

The test plan is the governing document for generating the test program and contains:

The Test Plan

• Binning information: devices might be binned into pass/fail or different pass grades (e.g., by maximum clock frequency). Continuity fails are binned separately, because they could be caused by contact issues of the handler or socket.

6.5 Types of Tests

6.5.1 Continuity Test

• A high voltage (running into the voltage limit) means no contact to the IC pin → open.
• A very small voltage means a short is detected at the IC pin → short.

The continuity test verifies the contact between the DIB and all pins of the DUT. As essentially all pins have some circuitry connected (at least the ESD protection diodes), a small current is forced into or out of each pin (with a voltage limit to protect the device in case of opens), and the resulting voltage is measured, as sketched in Figure 62:

Continuity Test

Figure 62: Continuity test: the tester forces a small current into the pin and measures the resulting voltage across the ESD protection diodes of the DUT.

Continuity test: the tester forces a small current into the pin and measures the resulting voltage across the ESD protection diodes of the DUT. A voltage near one diode drop confirms contact; a voltage running into the limit indicates an open, a near-zero voltage a short.

6.5.2 Leakage-Current Test

• A voltage is applied to all digital and analog inputs, and the current is measured.
• Digital outputs are set to high-Z (if possible), and the leakage current is measured as for the inputs.
• A voltage is applied to the \(V_\mathrm{DD}\) pins and the leakage current is measured; the device must be put into off-mode by applying the proper initialization (reset or power-on sequence).

A non-defective device draws only a small leakage current at the power-supply and I/O pins when in off-mode, so a leakage test is a fast method for detecting failing devices due to shorts and other misprocessing:

6.5.3 Memory Test

• Stuck-at faults (stuck-at-0, stuck-at-1) and transition faults (\(0 \rightarrow 1\) or \(1 \rightarrow 0\) not possible).
• Coupling faults (writing to one cell changes the content of another cell).
• Neighborhood pattern-sensitive faults.

Memory cells have to be tested for the following fault types caused by production defects:

Since on-chip memories can be large, memory testing can be costly, requiring a trade-off between fault coverage and test time. Example test methods:

Memory Test

• Zero-one (write all zeros, read all zeros, write all ones, read all ones)—\(\mathcal{O}(n)\).
• Checkerboard (write alternating 0101…, read, write the complement 1010…, read)—\(\mathcal{O}(n)\).
• Walking 1/0 (consecutively fill the memory with ones/zeros and check)—\(\mathcal{O}(n^2)\).
• ROM: read out and compute a checksum/CRC or hash—\(\mathcal{O}(n)\).

Applying these RAM tests can be done by external reads/writes (slow), by the internal CPU (faster), or by dedicated built-in self-test (BIST) hardware (fastest, at the cost of extra silicon area). Figure 63 shows the structure of a RAM BIST: a controller with pattern and address generators exercises the RAM, and a comparator checks the read-back data.

Memory Test

Figure 63: RAM built-in self-test (BIST): a controller sequences a test-pattern generator and an address generator that exercise the RAM through multiplexers; the read-back data is checked in a comparator, yielding a pass/fail result.

RAM built-in self-test (BIST): a controller sequences a test-pattern generator and an address generator that exercise the RAM through multiplexers; the read-back data is checked in a comparator, yielding a pass/fail result. In mission mode, the multiplexers connect the RAM to the normal system inputs.

6.5.4 JTAG Test and Debug Port

JTAG (IEEE Standard 1149.1) is a standardized test and debug port using serial communication to access IC-internal functional blocks (like the RAM BIST). JTAG uses four or five additional signals: TDI (test data in), TDO (test data out), TCK (test clock), TMS (test mode select), and optionally TRST (test reset). A two-pin version (cJTAG, IEEE 1149.7) uses only TMSC (test serial data) and TCKC (test clock).

JTAG was originally introduced to check interconnection faults on the PCB level, as solder joints are the main cause of failing boards: all IC pins can be forced to 0 or 1 (or read) via the boundary-scan chain, so all intended PCB connections between ICs can be tested after board manufacturing (see Figure 64). Meanwhile, JTAG is also extensively used to access internal components of an IC for debugging and test.

JTAG Test and Debug Port

Figure 64: JTAG boundary scan on a PCB: the boundary-scan cells (small squares) at every pin of each IC form a serial shift register; the chain runs from TDI through all devices to TDO, controlled by TCK and TMS.

JTAG boundary scan on a PCB: the boundary-scan cells (small squares) at every pin of each IC form a serial shift register; the chain runs from TDI through all devices to TDO, controlled by TCK and TMS. This allows forcing and observing all pins, and thus testing the PCB interconnects between the ICs.

6.5.5 Trimming

• If EEPROM bits are available, these can be used.
• Fuses (e.g., polysilicon or metal wires or minimum-size vias melted open) or anti-fuses (e.g., diodes melted into a short) can permanently store a bit by forcing a high current during programming.
• For analog precision circuits, laser trimming on the wafer can be used, e.g., to adjust the value of an integrated resistor.

If a property of the DUT needs to be trimmed (e.g., a reference voltage, an \(RC\) product, or an SRAM repair map), this property is measured on the tester. This might require a special test mode, where an internal signal is multiplexed to one of the pins, or an internal calibration circuit is triggered and the result is read out digitally. The resulting trimming information is permanently stored inside the DUT:

6.5.6 Scan-Path Test

• Observability: the ease of observing a node by watching the external output pins of the IC.
• Controllability: the ease of forcing a node to 0 or 1 by driving the input pins of the IC.

Digital circuits consist (besides RAM and ROM) of combinational logic and state machines. For testing, two properties of a circuit node matter:

Combinational circuits are controllable and observable, so it is relatively easy to determine test patterns. Sequential circuits, however, have states! Finite state machines can be very difficult to test, requiring many cycles to enter a desired state. Beyond a certain size, exhaustive testing with all possible input vectors becomes impractical: for a circuit with \(N\) inputs and \(M\) state bits, \(2^{N+M}\) patterns would be needed. For example, \(N = 40\) inputs and 32 states (\(M = 5\)) at 10 ns per pattern results in roughly 100 hours of test time.

Chip failures (opens, weak or strong shorts to other nodes) can cause very complex failure behavior, which is too time-consuming to test exhaustively—so a simplified stuck-at model is used: all failures are assumed to make nodes stuck at 0 (shorted to \(V_\mathrm{SS}\)) or stuck at 1 (shorted to \(V_\mathrm{DD}\)). This simple model is not quite true in reality, but works well enough in practice. Its limitation is demonstrated in Figure 65: an open in one pull-up branch of a CMOS NAND gate causes a sequential effect (the output keeps its previous value for one input combination), which needs two test vectors in the right order to be detected.

Scan-Path Test

Figure 65: Limitation of the stuck-at fault model: a CMOS NAND gate with an open defect in the pull-up path of \(B\).

Limitation of the stuck-at fault model: a CMOS NAND gate with an open defect in the pull-up path of \(B\). For \(A = 1\), \(B = 0\), neither the pull-up nor the pull-down network conducts, so the output floats and keeps its previous value \(Y_{n-1}\)—a sequential effect that requires two test vectors in the correct order to detect.

Scan-Path Test

• Each flip-flop is converted into a scan register (with a small area overhead): in mission mode, the flip-flops behave as usual; in scan mode, all flip-flops form a shift register, so their contents can be shifted in and out through dedicated pins.
• If each register can be observed and controlled this way, the test problem reduces to testing the combinational logic between the registers.

A manufacturing test would ideally check every node in the circuit, applying the smallest sequence of test vectors necessary to prove that each node is not stuck. To increase observability and controllability, i.e., design for test (DFT), the scan-path test is introduced, shown in Figure 66:

Scan-Path Test

• During the production test, test patterns are shifted into the scan chains, one clock cycle is applied, and the captured result is shifted out and compared to the expected result (→ pass/fail). Digital pattern generators in the ATE hardware accelerate this.
• The patterns are generated automatically by software (ATPG) from the design netlist, achieving high stuck-at fault coverage with a minimum number of patterns.

Scan-Path Test

• To speed up testing further, multiple chains are operated in parallel (requiring test pins for the parallel chain inputs and outputs).
• An extension of scan is to use internal pattern generators (e.g., based on a pseudo-random number generator) as logic inputs, and to compress the outputs into a syndrome (e.g., a transition count or hash) that is compared to the expected syndrome → logic BIST.

Scan-Path Test

Figure 66: Scan-path test: every flip-flop is replaced by a scan flip-flop with an input multiplexer.

Scan-path test: every flip-flop is replaced by a scan flip-flop with an input multiplexer. In mission mode (scan enable SE = 0), the flip-flops capture the outputs of the combinational logic; in scan mode (SE = 1), all flip-flops form a shift register from scan-in (SI) to scan-out (SO), making every register controllable and observable.

6.5.7 AC Parametric Tests

Analog and mixed-signal parametric tests are highly dependent on the given function; examples are gain, phase, distortion, rejection (CMRR, PSRR), and noise. The DIB must be designed to reflect the conditions of the IC datasheet, e.g., applying the proper output loading (\(R\) and \(C\)); different loads for different tests can be switched in via relays. Noise tests can be very time-consuming due to the long averaging needed to detect small signals; additional circuitry on the DIB can help to increase repeatability and speed.

Modern mixed-signal testers use arbitrary waveform generators (AWGs) and digitizers to create and capture analog signals, with DSPs to speed up signal generation and analysis, as shown in Figure 67. Concepts from sampling theory (quantization noise, under/oversampling, aliasing and reconstruction, FFT, windowing, sampling-clock coherence, etc.) apply!

AC Parametric Tests

Figure 67: Mixed-signal AC parametric test setup: an arbitrary waveform generator (AWG) synthesizes the stimulus from a pattern memory, the DUT response is captured by a digitizer, and a DSP evaluates the records (FFT, filtering, averaging).

Mixed-signal AC parametric test setup: an arbitrary waveform generator (AWG) synthesizes the stimulus from a pattern memory, the DUT response is captured by a digitizer, and a DSP evaluates the records (FFT, filtering, averaging). A common, coherent clock for AWG and digitizer avoids spectral leakage.

6.6 Process Capability Index

For analog test parameters, the variation over production must stay inside the test limits, which are derived from the datasheet limits minus guard bands: the lower specification limit (LSL) and the upper specification limit (USL).

Process Capability Index

\[ \overline{X} = \frac{1}{N} \sum_{i=1}^{N} x_i \qquad \sigma = \sqrt{\frac{1}{N} \sum_{i=1}^{N} \left( x_i - \overline{X} \right)^2} \]

\[ C_\mathrm{p} = \frac{\mathrm{USL} - \mathrm{LSL}}{6 \sigma} \tag{55}\]

To manufacture within a specification, the difference between the USL and the LSL must be greater than the total process variation, and the distribution should be well centered between the limits. One way to check this is the \(C_\mathrm{p}\)/\(C_\mathrm{pk}\) analysis (Montgomery 2012). Given a parameter distribution \(x_i\) from a sample of size \(N\), the arithmetic mean and the standard deviation are

Then, the process capability indices are calculated as

Process Capability Index

\[ C_\mathrm{pk} = \min \left\lbrace \frac{\mathrm{USL} - \overline{X}}{3 \sigma}, \frac{\overline{X} - \mathrm{LSL}}{3 \sigma} \right\rbrace \tag{56}\]

\(C_\mathrm{p}\) measures whether the process spread fits between the limits at all, while \(C_\mathrm{pk}\) additionally accounts for the centering of the distribution. Ideally, \(C_\mathrm{p} = C_\mathrm{pk}\) (the process is well centered), and \(C_\mathrm{pk} > 2\) (which might not be achievable, so lower values like \(C_\mathrm{pk} > 1.5\) may have to be accepted). Figure 68 illustrates well-centered and off-center distributions.

During product qualification, the \(C_\mathrm{p}\)/\(C_\mathrm{pk}\) values are evaluated on a sufficient sample size, and critical tests are improved (change of datasheet limits, better centering of a parameter by redesign, process centering, etc.).

Process Capability Index

Figure 68: Process capability: (a) a well-centered distribution with small spread (\(C_\mathrm{p} = C_\mathrm{pk} = 2\)); (b) the same spread but off-center—\(C_\mathrm{p}\) is unchanged, but \(C_\mathrm{pk}\) drops to 1, indicating parts close to the upper specification limit; (c) a centered but wide distribution, where both indices are poor and yield is lost at both limits.

References

Bhunia, Swarup, and Mark Tehranipoor. 2018. Hardware Security: A Hands-on Learning Approach. Morgan Kaufmann.

Montgomery, Douglas C. 2012. Introduction to Statistical Quality Control. 7th ed. Wiley.

Wang, Laung-Terng, Cheng-Wen Wu, and Xiaoqing Wen, eds. 2006. VLSI Test Principles and Architectures: Design for Testability. Morgan Kaufmann.

The advantage of using the \(C_\mathrm{p}\)/\(C_\mathrm{pk}\) analysis is that it provides a quantitative measure of both the process spread and the centering of the distribution relative to the specification limits. This helps in automatically identifying whether the process is capable of consistently producing parts within the desired specifications and whether any adjustments are needed to improve yield and quality with just two numbers: \(C_\mathrm{p}\) and \(C_\mathrm{pk}\). Manual inspection of the distribution alone may not reveal subtle misalignments or variations that could impact production quality and can be extremely time consuming and error prone.

References