The MOSFET

Design of Complex Integrated Circuits

2 The MOSFET

2.1 MOSFET Operation in a Nutshell

This chapter on the metal-oxide-semiconductor field-effect transistor (MOSFET) is largely based on (Hu 2010; Razavi 2014; Tsividis and McAndrew 2011), which are also recommended as further reading. In contrast to our Analog Circuit Design course, where we treated the MOSFET essentially as a numerically-characterized black box, we will derive a simple, first-order model of the MOSFET from the physics of the device, and then discuss the most important second-order effects. The goal is to understand the basic operation of the MOSFET and its \(I\)/\(V\) characteristic, which will be used in later chapters for circuit design.

MOSFET Operation in a Nutshell

Doping Notation

In the doping notation, \(+\) indicates a higher doping concentration than the surrounding material, while \(++\) indicates an even higher doping concentration. For example, \(n^+\)-doped regions have a higher electron concentration than the \(n\)-type substrate, and \(n^{++}\)-doped gates have an even higher electron concentration than the \(n^+\)-doped source/drain regions.

The basic MOSFET structure consists of a gate (terminal \(G\)) that is insulated from a doped semiconductor and controls the surface charge in the semiconductor channel below, between the source (terminal \(S\)) and the drain (terminal \(D\)). The source provides the charge carriers, and an electric field pulls them toward the drain (hence a semiconductor device based on drift current). The electric potential of the semiconductor bulk (terminal \(B\)) acts on the channel as well and is the fourth terminal of the MOSFET. Ideally, the effect of the bulk is negligible.

Two complementary flavors of the device exist: the \(n\)-type MOSFET (“NMOS”) has \(n^+\)-doped source/drain regions on a \(p\)-type substrate and usually an \(n^{++}\)-doped gate, while the \(p\)-type MOSFET (“PMOS”) has \(p^+\)-doped source/drain regions in an \(n\)-type well and usually a \(p^{++}\)-doped gate.

MOSFET Operation in a Nutshell

Figure 4: Cross section of an NMOS transistor for increasing gate voltage (drain and source grounded): (a) flatband condition, (b) gate at 0 V, (c) gate below the threshold voltage, and (d) inversion.

To understand the operation of the NMOS transistor, it is instructive to follow the conditions in the semiconductor while the gate voltage is swept upwards, as illustrated in Figure 4:

Cross section of an NMOS transistor for increasing gate voltage (drain and source grounded): (a) flatband condition, (b) gate at 0 V, (c) gate below the threshold voltage, and (d) inversion. The dashed line marks the depletion-region boundary, circled minus signs are ionized acceptors, plus signs are holes, and the dark blue layer in (d) is the electron inversion layer.

MOSFET Operation in a Nutshell

• Flatband (a): When the gate is at a specific negative voltage (the flatband voltage \(V_\mathrm{fb}\)), and all other terminals are at \(0\,\text{V}\), a depletion zone forms only around the drain and source junctions. No current can flow, since drain and source are \(n^+\)-doped while the substrate is \(p\)-type, so the two junctions form back-to-back diodes.

MOSFET Operation in a Nutshell

• Zero gate voltage (b): When the gate voltage is increased to \(0\,\text{V}\), a depletion zone also forms below the gate. The \(p\)-type acceptor ions in this region have captured an electron and are thus immobile, negatively charged sites (illustrated by the circled minus symbols)—still, no current can flow.

MOSFET Operation in a Nutshell

• Below threshold (c): When the gate voltage increases further (but stays below the threshold voltage), the depletion zone below the gate deepens, reaching a maximum depletion width \(W_\mathrm{dep}\) when \(V_\mathrm{GS}= V_\mathrm{th}\). There is still no conduction between drain and source, because there are no (or at least very few) free electrons in the channel region.

MOSFET Operation in a Nutshell

• Inversion (d): When the gate voltage rises above the threshold voltage \(V_\mathrm{th}\), inversion occurs: a thin layer of free electrons forms directly below the gate oxide, creating a conducting channel of electrons between drain and source. The source of the electrons in the inversion layer is the \(n^+\)-doped source region, which is connected to ground.

MOSFET Operation in a Nutshell

• The electrons are pulled from the source into the channel by the positive gate voltage, and they can now flow to the drain if a drain voltage is applied.

Once the channel exists, the drain voltage determines the mode of conduction, as shown in Figure 5:

MOSFET Operation in a Nutshell

Figure 5: Cross section of an NMOS transistor in inversion for increasing drain voltage: (a) triode region, where the inversion layer extends from source to drain, and (b) saturation, where the channel is pinched off at the drain side.

MOSFET Operation in a Nutshell

• Triode (a): If a small voltage is applied between drain and source, a current flows, and the depletion zone around the drain widens. The drain current is a function of both \(V_\mathrm{GS}\) and \(V_\mathrm{DS}\); the device operates in the triode region. The MOSFET operates like a voltage-controlled resistor in this region.

MOSFET Operation in a Nutshell

• Saturation (b): If the drain-source voltage is increased beyond \(V_\mathrm{DS}> V_\mathrm{GS}- V_\mathrm{th}\), the channel is pinched off at the drain side, and the drain current is (to first order) no longer a function of \(V_\mathrm{DS}\), only of \(V_\mathrm{GS}\)—the device is now in saturation. The MOSFET operates like a voltage-controlled current source in this region.

2.1.1 An Exemplary 130 nm Process Technology

Table 1: Typical parameters of the IHP SG13 130 nm CMOS technology

Parameter	Symbol	Typical value
Nominal supply voltage	\(V_\mathrm{DD}\)	1.2 V (digital) / 1.5 V (analog)
Minimum gate length	\(L_\mathrm{min}\)	130 nm
Oxide thickness	\(t_\mathrm{ox}\)	2 nm
Threshold voltage NMOS | PMOS	\(V_\mathrm{th,n}\) | \(V_\mathrm{th,p}\)	0.5 V | −0.47 V
Maximum voltage	\(|V_\mathrm{GS,max}|\), \(|V_\mathrm{DS,max}|\)	2 V
Gate capacitance	\(C'_\mathrm{ox}\)	17.3 fF/µm²
Process constant \(K_\mathrm{n}\) | \(K_\mathrm{p}\)	\(\mu_\mathrm{n}C'_\mathrm{ox}\) | \(\mu_\mathrm{p}C'_\mathrm{ox}\)	280 µA/V² | 130 µA/V²

Throughout this text we will use typical parameters of a 0.13 µm CMOS process technology, specifically IHP SG13 (process specification), for exemplary calculations. The key parameters are listed in Table 1.

2.2 Basic I/V Characteristic of the MOSFET

2.2.1 The MOS Capacitor and the Threshold Voltage

\[ \frac{d^2 \Phi(y)}{d y^2} = -\frac{\rho(y)}{\varepsilon_\mathrm{si}} = \frac{q N_\mathrm{a}}{\varepsilon_\mathrm{si}} \quad \rightarrow \quad \Phi(y) = \frac{q N_\mathrm{a}}{2 \varepsilon_\mathrm{si}} y^2 \tag{1}\]

\[ W_\mathrm{dep}= \sqrt{\frac{2 \varepsilon_\mathrm{si}\Phi_\mathrm{S}}{q N_\mathrm{a}}}. \tag{2}\]

If source, drain, and substrate are grounded (\(V_\mathrm{S} = V_\mathrm{D} = V_\mathrm{B} = 0\,\text{V}\)), and a positive voltage \(V_\mathrm{GS}= V_\mathrm{G}\) is applied to the gate, then positive charge accumulates on the gate and negative charge in the \(p\)-type substrate, forming a depletion layer in the substrate.

If we assume a uniform charge density \(\rho = -q N_\mathrm{a}\) across this layer with \(N_\mathrm{a}\) being the doping concentration of the \(p\)-type substrate (in a practical device, this charge density is not uniform), then we can use Poisson’s equation. Note that with the boundary conditions assuming \(\Phi(0) = 0\) and \(d\Phi(0)/dy = 0\), \(y=0\) is the point where the depletion layer starts in the depth of the substrate, and \(y = W_\mathrm{dep}\) is the point where the depletion layer ends (the depletion width) at the substrate-oxide interface (\(\varepsilon_\mathrm{si}\) is the permittivity of silicon):

The surface potential \(\Phi_\mathrm{S}= \Phi(W_\mathrm{dep})\) at the oxide-silicon interface is then related to the depletion width \(W_\mathrm{dep}\) by

With \(W_\mathrm{dep}\) we can also calculate the corresponding depletion capacitance (per unit area, indicated with the prime):

The MOS Capacitor and the Threshold Voltage

\[ C'_\mathrm{dep}= \frac{\varepsilon_\mathrm{si}}{W_\mathrm{dep}} = \sqrt{\frac{q N_\mathrm{a}\varepsilon_\mathrm{si}}{2 \Phi_\mathrm{S}}} \tag{3}\]

\[ Q'_\mathrm{dep} = - q N_\mathrm{a}W_\mathrm{dep}= - \sqrt{2 q N_\mathrm{a}\varepsilon_\mathrm{si}\Phi_\mathrm{S}} \tag{4}\]

The charge per unit area \(Q'_\mathrm{dep}\) in this region is (negative, because of the captured electrons)

The gate voltage is the result of the sum of the flatband voltage, the surface potential, and the voltage across the oxide

The MOS Capacitor and the Threshold Voltage

\[ V_\mathrm{G} = \Phi_\mathrm{fb}+ \Phi_\mathrm{S}+ V_\mathrm{ox} = \Phi_\mathrm{fb0} + \frac{-Q'_\mathrm{ss}}{C'_\mathrm{ox}} + \Phi_\mathrm{S}+ \frac{-Q'_\mathrm{sub}}{C'_\mathrm{ox}} \tag{5}\]

\[ V_\mathrm{G} = \Phi_\mathrm{fb}+ \frac{q N_\mathrm{a}W_\mathrm{dep}^2}{2 \varepsilon_\mathrm{si}} + \frac{q N_\mathrm{a}W_\mathrm{dep}}{C'_\mathrm{ox}} \tag{6}\]

where \(\Phi_\mathrm{fb}\) is the work-function difference between the gate and the substrate material (the flatband voltage \(V_\mathrm{fb}\) used in Figure 4). Note that the negative sign in the last term arises because voltage and charge are taken from different electrodes of the gate capacitor: the voltage \(V_\mathrm{ox}\) at the top, and the substrate charge \(Q'_\mathrm{sub}\) as well as the interface charge \(Q'_\mathrm{ss}\) at the bottom.

An interface charge \(Q'_\mathrm{ss}\) can be present at the SiO₂-Si interface due to crystal discontinuities. This interface charge can be accounted for by adapting the flatband voltage \(\Phi_\mathrm{fb0}\) to \(\Phi_\mathrm{fb}\) (going forward, we will just use \(\Phi_\mathrm{fb}\)).

Using Equation 2 to express \(\Phi_\mathrm{S}= q N_\mathrm{a}W_\mathrm{dep}^2 / (2 \varepsilon_\mathrm{si})\) and Equation 4 for \(Q'_\mathrm{sub} = Q'_\mathrm{dep}\), Equation 5 can be written as

From Equation 6, the depletion width \(W_\mathrm{dep}\) can be calculated as a function of \(V_\mathrm{G}\), and from this \(\Phi_\mathrm{S}= f(V_\mathrm{G})\) using Equation 2.

If the surface potential \(\Phi_\mathrm{S}\) reaches a critical level of twice the Fermi potential \(\Phi_\mathrm{B}\), then inversion occurs: a thin layer of electrons is induced directly under the oxide. The gate voltage that is minimally required to produce this inversion layer is called the threshold voltage \(V_\mathrm{th}= V_\mathrm{G}(\Phi_\mathrm{S}= 2 \Phi_\mathrm{B})\).

The MOS Capacitor and the Threshold Voltage

\[ V_\mathrm{th}= \Phi_\mathrm{fb}+ 2 \Phi_\mathrm{B}+ \frac{-Q'_\mathrm{dep}}{C'_\mathrm{ox}} = \Phi_\mathrm{fb}+ 2 \Phi_\mathrm{B}+ \frac{\sqrt{2 q N_\mathrm{a}\varepsilon_\mathrm{si}\cdot 2 \Phi_\mathrm{B}}}{C'_\mathrm{ox}} \tag{7}\]

\[ \Phi_\mathrm{B}= \frac{k T}{q} \ln \frac{N_\mathrm{a}}{n_\mathrm{i}}. \tag{8}\]

with the Fermi potential

Figure 6 illustrates the flatband and the threshold condition in terms of the energy bands of the MOS structure.

The MOS Capacitor and the Threshold Voltage

Figure 6: Simplified energy-band diagram of the MOS structure (\(n^{++}\)-poly gate, oxide, \(p\)-substrate): (a) at the flatband condition, where the bands in the silicon are flat, and (b) at the threshold condition, where the bands at the surface are bent down by \(2\Phi_\mathrm{B}\) and inversion sets in (band bending shown qualitatively).

Simplified energy-band diagram of the MOS structure (\(n^{++}\)-poly gate, oxide, \(p\)-substrate): (a) at the flatband condition, where the bands in the silicon are flat, and (b) at the threshold condition, where the bands at the surface are bent down by \(2\Phi_\mathrm{B}\) and inversion sets in (band bending shown qualitatively). The green arrow marks the applied gate voltage \(V_\mathrm{G}\), which shifts the gate Fermi level by \(-qV_\mathrm{G}\) against the bulk Fermi level; in (a) \(V_\mathrm{G} = V_\mathrm{FB} < 0\), in (b) \(V_\mathrm{G} = V_\mathrm{th} > 0\). The blue shading in (b) marks the inversion layer of electrons at the surface.

The MOS Capacitor and the Threshold Voltage

Note 1: Example Calculation of the Threshold Voltage

Let us assume a substrate doping level of \(N_\mathrm{a}= 3 \times 10^{18}\,\text{cm}^{-3}\). The Fermi potential can be calculated with Equation 8 (using the intrinsic carrier concentration of silicon \(n_\mathrm{i} = 1.0 \times 10^{10}\,\text{cm}^{-3}\) at room temperature \(T = 300\,\text{K}\)):

\[ \Phi_\mathrm{B}= \frac{k T}{q} \ln \frac{N_\mathrm{a}}{n_\mathrm{i}} = 0.50\,\text{V} \]

We further use \(C'_\mathrm{ox}= \varepsilon_\mathrm{ox}/ t_\mathrm{ox}= 17.3\,\text{fF}/\mu\text{m}^2\) for a \(t_\mathrm{ox}= 2\,\text{nm}\) gate oxide. The flatband voltage for an \(n^+\)-polysilicon gate on the \(p\)-substrate with doping \(N_\mathrm{a}\) is (with the silicon band-gap voltage \(\Phi_\mathrm{bg} = 1.12\,\text{V}\))

\[ \Phi_\mathrm{fb}= -\frac{\Phi_\mathrm{bg}}{2} - \Phi_\mathrm{B}= -1.06\,\text{V} \]

The resulting threshold voltage is thus (beware of units!)

\[ V_\mathrm{th}= \Phi_\mathrm{fb}+ 2 \Phi_\mathrm{B}+ \frac{\sqrt{2 q N_\mathrm{a}\varepsilon_\mathrm{si}\cdot 2 \Phi_\mathrm{B}}}{C'_\mathrm{ox}} = 0.53\,\text{V} \]

The MOS Capacitor and the Threshold Voltage

Example Calculation of the Threshold Voltage

Using these values, we can also calculate the depletion width \(W_\mathrm{dep}\) in inversion, and the corresponding \(C'_\mathrm{dep}\) (compare \(W_\mathrm{dep}\) to \(t_\mathrm{ox}\), and \(C'_\mathrm{dep}\) to \(C'_\mathrm{ox}\)):

\[ W_\mathrm{dep}= \sqrt{\frac{2 \varepsilon_\mathrm{si}\cdot 2 \Phi_\mathrm{B}}{q N_\mathrm{a}}} = 21.0\,\text{nm} \quad \text{and} \quad C'_\mathrm{dep}= \frac{\varepsilon_\mathrm{si}}{W_\mathrm{dep}} = 5.0\,\text{fF}/\mu\text{m}^2 \]

The MOS Capacitor and the Threshold Voltage

Figure 7: Depletion width \(W_\mathrm{dep}\) (left) and surface potential \(\Phi_\mathrm{S}\) (right) as a function of the gate potential \(V_\mathrm{G}\), calculated with the depletion approximation for \(N_\mathrm{a} = 3 \times 10^{18}\,\mathrm{cm}^{-3}\), \(t_\mathrm{ox} = 2\,\)nm, and \(\Phi_\mathrm{fb} = -1.05\,\)V.

Using Equation 6 and Equation 2 we can now visualize the depletion width \(W_\mathrm{dep}\) and the surface potential \(\Phi_\mathrm{S}\) as a function of the gate potential \(V_\mathrm{G}\), shown in Figure 7. Note how the surface potential saturates at \(2\Phi_\mathrm{B}\) once inversion is reached: any additional gate charge is then mirrored by electrons in the inversion layer rather than by a deeper depletion region.

Depletion width \(W_\mathrm{dep}\) (left) and surface potential \(\Phi_\mathrm{S}\) (right) as a function of the gate potential \(V_\mathrm{G}\), calculated with the depletion approximation for \(N_\mathrm{a} = 3 \times 10^{18}\,\mathrm{cm}^{-3}\), \(t_\mathrm{ox} = 2\,\)nm, and \(\Phi_\mathrm{fb} = -1.05\,\)V. Once inversion is reached at \(\Phi_\mathrm{S} = 2\Phi_\mathrm{B}\) (at \(V_\mathrm{G} = V_\mathrm{th} \approx 0.5\,\)V), both quantities saturate.

2.2.2 Derivation of the I/V Characteristic

\[ I_\mathrm{D}= W Q'_\mathrm{inv} v = W Q'_\mathrm{inv} \mu_\mathrm{n}E = W Q'_\mathrm{inv} \mu_\mathrm{n}\frac{V_\mathrm{DS}}{L} = \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} (V_\mathrm{GS}- V_\mathrm{th}) V_\mathrm{DS} \tag{9}\]

\[ I_\mathrm{D}= W Q'_\mathrm{inv}(x) v = W C'_\mathrm{ox}( V_\mathrm{GS}- V_\mathrm{cs} - V_\mathrm{th}) \mu_\mathrm{n}\frac{dV_\mathrm{cs}}{dx} \]

If we now apply a small \(V_\mathrm{DS}\), then a sufficiently large \(V_\mathrm{GS}> V_\mathrm{th}\) builds up the inversion charge \(Q'_\mathrm{inv} = C'_\mathrm{ox}(V_\mathrm{GS}- V_\mathrm{th})\) in the channel below the gate, which is then moved from source to drain by the electric field caused by \(V_\mathrm{DS}\), resulting in the drift current \(I_\mathrm{D}\) (\(\mu_\mathrm{n}\) is the electron mobility):

If \(V_\mathrm{DS}\) increases further, the channel charge \(Q'_\mathrm{inv}(x)\) becomes a function of the position in the channel, because the drain current causes a potential gradient \(dV_\mathrm{cs}/dx\) along the channel (we assume that \(V_\mathrm{DS}\) is small enough so that the whole channel is still inverted). \(x=0\) is the source end of the channel, and \(x=L\) is the drain end.

Integrating along the channel from source to drain,

Derivation of the I/V Characteristic

\[ \int_{0}^{L} I_\mathrm{D}\, dx = \mu_\mathrm{n}C'_\mathrm{ox}W \int_{0}^{V_\mathrm{DS}} ( V_\mathrm{GS}- V_\mathrm{cs} - V_\mathrm{th}) \, dV_\mathrm{cs}, \]

\[ I_\mathrm{D}= \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} \left[ ( V_\mathrm{GS}- V_\mathrm{th}) V_\mathrm{DS}- \frac{1}{2} V_\mathrm{DS}^2 \right]. \tag{10}\]

yields the well-known square-law characteristic

Note that this simple derivation of the MOSFET I/V characteristic is only valid for long-channel devices (\(L > 1\,\mu\text{m}\)) and does not account for second-order effects such as channel-length modulation, body effect, velocity saturation, mobility degradation with the vertical field, and subthreshold conduction. These effects will be discussed in the next section.

2.2.3 Triode Region

\[ V_\mathrm{od}= V_\mathrm{GS}- V_\mathrm{th} \tag{11}\]

\[ I_\mathrm{D}\approx \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} ( V_\mathrm{GS}- V_\mathrm{th}) V_\mathrm{DS}\quad \rightarrow \quad g_\mathrm{ds}= \frac{1}{r_\mathrm{o}}= \frac{\partial I_\mathrm{D}}{\partial V_\mathrm{DS}} = \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} ( V_\mathrm{GS}- V_\mathrm{th}) \tag{12}\]

Equation 10 is valid only for classical, long-channel (\(L > 1\,\mu\text{m}\)) devices, and only as long as \(V_\mathrm{DS}\leq V_\mathrm{GS}- V_\mathrm{th}= V_\mathrm{od}\); this range of operation is the so-called triode region. The overdrive voltage

is a frequently used quantity. The ratio \(W/L\) is a dimensionless quantity called the aspect ratio of the MOSFET—note that only the relative sizing of \(W\) and \(L\) impacts the transistor’s \(I\)/\(V\) characteristic!

For \(V_\mathrm{DS}\ll V_\mathrm{GS}- V_\mathrm{th}\), we can simplify Equation 10 and see that the MOSFET behaves like a voltage-controlled resistor:

Figure 8 shows the resulting output characteristic in the triode region for three different gate voltages.

Triode Region

Figure 8: NMOS output characteristic in the triode region according to the square-law model (\(\mu_\mathrm{n} C'_\mathrm{ox} = 280\,\mathrm{\mu A/V^2}\), \(W/L = 10\), \(V_\mathrm{th} = 0.5\,\)V).

NMOS output characteristic in the triode region according to the square-law model (\(\mu_\mathrm{n} C'_\mathrm{ox} = 280\,\mathrm{\mu A/V^2}\), \(W/L = 10\), \(V_\mathrm{th} = 0.5\,\)V). Each curve ends at the edge of saturation, \(V_\mathrm{DS} = V_\mathrm{GS} - V_\mathrm{th}\).

2.2.4 Saturation Region

\[ I_\mathrm{D}= I_\mathrm{DS,sat} = \frac{1}{2} \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} ( V_\mathrm{GS}- V_\mathrm{th})^2 \tag{13}\]

\[ g_\mathrm{m}= \frac{\partial I_\mathrm{D}}{\partial V_\mathrm{GS}}, \]

If \(V_\mathrm{DS}> V_\mathrm{GS}- V_\mathrm{th}\), the assumption of a completely inverted channel leading up to Equation 10 is no longer valid. The channel gets pinched off at the drain side; this happens at \(V_\mathrm{DS,sat} = V_\mathrm{GS}- V_\mathrm{th}\), leading to a maximum (saturated) value of the drain current. Substituting \(V_\mathrm{DS}= V_\mathrm{DS,sat}\) into Equation 10 gives the drain current in the saturation region:

In the saturation region, the MOSFET behaves like a voltage-controlled current source, so it is useful to define the transconductance

which can be expressed in various forms:

Saturation Region

\[ g_\mathrm{m}= \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} (V_\mathrm{GS}-V_\mathrm{th}) = \sqrt{2 \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} I_\mathrm{D}} = \frac{2 I_\mathrm{D}}{V_\mathrm{GS}-V_\mathrm{th}} \tag{14}\]

We see that \(g_\mathrm{m}\) is a linear function of the overdrive \(V_\mathrm{od}= V_\mathrm{GS}- V_\mathrm{th}\) (leading to a quadratic rise of the drain current), or a square-root function of \(I_\mathrm{D}\), or simply the drain current divided by half the overdrive voltage. Note that for a BJT \(g_\mathrm{m}= I_\mathrm{C} / V_\mathrm{T}\), so the MOSFET offers more degrees of freedom. Figure 9 shows the complete output characteristic including the boundary between triode and saturation.

Saturation Region

Figure 9: Complete NMOS output characteristic according to the square-law model (\(\mu_\mathrm{n} C'_\mathrm{ox} = 280\,\mathrm{\mu A/V^2}\), \(W/L = 10\), \(V_\mathrm{th} = 0.5\,\)V).

Complete NMOS output characteristic according to the square-law model (\(\mu_\mathrm{n} C'_\mathrm{ox} = 280\,\mathrm{\mu A/V^2}\), \(W/L = 10\), \(V_\mathrm{th} = 0.5\,\)V). The dashed red line marks the boundary \(V_\mathrm{DS} = V_\mathrm{GS} - V_\mathrm{th}\) between the triode and the saturation region.

2.2.5 Complementary MOS (CMOS)

In CMOS technologies, both NMOS and PMOS devices are needed and fabricated on the same wafer, as shown in Figure 10. Usually, the PMOS is located in a local \(n\)-well, and this \(n\)-well is tied to the most positive supply voltage (\(V_\mathrm{DD}\)), while the \(p\)-substrate is tied to ground (\(V_\mathrm{SS}\)). The substrate contacts are realized with \(p^+\)-diffusions in the \(p\)-substrate (forming an ohmic contact), and the well contacts are realized with \(n^+\)-diffusions in the \(n\)-well.

For increased isolation (especially for analog applications), a triple-well (or “deep \(n\)-well,” DNW) option is sometimes available; the NMOS is then located in a local \(p\)-well which is fully enclosed by an \(n\)-well and thus isolated from the common substrate.

Complementary MOS (CMOS)

Figure 10: NMOS and PMOS transistors integrated on a single wafer: the NMOS sits directly in the p-substrate, the PMOS in a local n-well.

NMOS and PMOS transistors integrated on a single wafer: the NMOS sits directly in the p-substrate, the PMOS in a local n-well. The p\(^+\) substrate contact ties the substrate to \(V_\mathrm{SS}\), the n\(^+\) well contact ties the n-well to \(V_\mathrm{DD}\).

Complementary MOS (CMOS)

Figure 11: The CMOS inverter: (a) schematic and (b) the same circuit in the cross-section of the wafer.

In Figure 11, we see a simple CMOS inverter consisting of a PMOS and an NMOS transistor. The PMOS is connected to the positive supply voltage \(V_\mathrm{DD}\), while the NMOS is connected to ground \(V_\mathrm{SS}\). The gates of both transistors are tied together and form the input \(A\) of the inverter, while the drains are also tied together and form the output \(Y\). When the input is low, the PMOS is on and the NMOS is off, pulling the output high. Conversely, when the input is high, the PMOS is off and the NMOS is on, pulling the output low.

The CMOS inverter: (a) schematic and (b) the same circuit in the cross-section of the wafer. The PMOS pulls the output \(Y\) up when the input \(A\) is low, the NMOS pulls it down when the input is high, so in the static state no dc current flows from \(V_\mathrm{DD}\) to \(V_\mathrm{SS}\). The bulk of the PMOS (its \(n\)-well) is tied to \(V_\mathrm{DD}\), the bulk of the NMOS (the \(p\)-substrate) to \(V_\mathrm{SS}\). In (b) the hop marks a wire crossing without contact, which in a real chip is realized on two different metal layers.

2.3 Second-Order Effects in the MOSFET

Note that in the CMOS technology shown in Figure 11, the bulk nodes of all the NMOS transistors are tied to the common substrate (\(V_\mathrm{SS}\)), while the bulk nodes of all the PMOS transistors are tied to the \(n\)-well (\(V_\mathrm{DD}\)). Since the \(n\)-wells are separated from the substrate (and can be separated between different PMOS devices), the bulk nodes of selected PMOS can be tied to different potentials than \(V_\mathrm{DD}\) (e.g., to the source of the PMOS), which is called body biasing. This can be used to adjust the threshold voltage of the PMOS transistors or to avoid the bulk effect (see Section 2.3.1).

2.3.1 Body Effect

\[ V_\mathrm{th}= V_\mathrm{th0} + \gamma \left( \sqrt{2 \Phi_\mathrm{B}+ V_\mathrm{SB}} - \sqrt{2 \Phi_\mathrm{B}} \right) \tag{15}\]

\[ \gamma = \frac{\sqrt{2 q N_\mathrm{a}\varepsilon_\mathrm{si}}}{C'_\mathrm{ox}} = 2 (n - 1) \sqrt{2 \Phi_\mathrm{B}}. \tag{16}\]

The simple MOSFET model developed so far is only valid to first order for long-channel devices (\(L_\mathrm{min} > 1\,\mu\text{m}\)) under idealistic conditions. In the following, we discuss the most important second-order effects: the body effect, channel-length modulation, velocity saturation, mobility degradation with the vertical field, and subthreshold conduction.

In the derivation of Equation 7 we tied source, drain, and bulk together. Note that the inversion charge is a function of the bulk (substrate) potential \(V_\mathrm{B}\) versus the gate potential \(V_\mathrm{G}\), so when the source potential \(V_\mathrm{S}\) differs from \(V_\mathrm{B}\), the apparent \(V_\mathrm{th}\) becomes a function of \(V_\mathrm{SB}\), because inversion is reached at a surface potential of \(2 \Phi_\mathrm{B}+ V_\mathrm{SB}\) instead of \(2 \Phi_\mathrm{B}\).

This is the so-called body effect (or “back-gate effect”). The effective threshold voltage is given by (\(V_\mathrm{th0}\) is the threshold voltage with \(V_\mathrm{SB}= 0\))

with the body-effect coefficient \(\gamma\) (the factor \(n\) will be introduced in Section 2.3.5)

Note that for \(n = 1\) (no body effect), \(\gamma = 0\) and thus \(V_\mathrm{th}= V_\mathrm{th0}\).

Body Effect

Note 2: Example Calculation of the Body Effect (NMOS)

Starting with the previously used values (\(N_\mathrm{a}= 3 \times 10^{18}\,\text{cm}^{-3}\), \(C'_\mathrm{ox}= 17.3\,\text{fF}/\mu\text{m}^2\), \(\Phi_\mathrm{B}= 0.50\,\text{V}\)), we get

\[ \gamma = \frac{\sqrt{2 q N_\mathrm{a}\varepsilon_\mathrm{si}}}{C'_\mathrm{ox}} = 0.58\,\text{V}^{1/2} \]

Let us consider the originally calculated \(V_\mathrm{th0} = 0.53\,\text{V}\) and assume the bulk is tied to \(V_\mathrm{SS}= V_\mathrm{B} = 0\,\text{V}\) while the source sits at \(V_\mathrm{S} = 0.5\,\text{V}\) (so \(V_\mathrm{SB}= 0.5\,\text{V}\)). Using Equation 15:

\[ V_\mathrm{th}= 0.53 + 0.58 \left( \sqrt{2 \cdot 0.50 + 0.5} - \sqrt{2 \cdot 0.50} \right) = 0.66\,\text{V} \]

Body Effect

Example Calculation of the Body Effect (NMOS)

In this case, the threshold voltage has been increased by 130 mV. Conversely, by tying the bulk to a higher potential than the source, the threshold voltage can also be decreased, but beware of the risk of forward-biasing the source-bulk pn-junction (see Figure 10)!

2.3.2 Channel-Length Modulation

\[ I_\mathrm{D}= \frac{1}{2} \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} ( V_\mathrm{GS}- V_\mathrm{th})^2 (1 + \lambda V_\mathrm{DS}) \tag{17}\]

\[ g_\mathrm{ds}= \frac{\partial I_\mathrm{D}}{\partial V_\mathrm{DS}} = I_\mathrm{D}\rvert_{\lambda = 0} \cdot \lambda \tag{18}\]

In the derivation of the saturation current (Equation 13), we assumed that the channel is pinched off exactly at the drain when \(V_\mathrm{DS}= V_\mathrm{GS}- V_\mathrm{th}\). When \(V_\mathrm{DS}\) is increased further, this pinch-off point moves away from the drain towards the source. This can be viewed as an effective channel-length reduction, \(L_\mathrm{eff} = f(V_\mathrm{DS}) < L\), and we have to use \(L_\mathrm{eff}\) instead of \(L\) in Equation 13. Avoiding a direct calculation of \(L_\mathrm{eff}\), it is common to set \(1/L_\mathrm{eff} \approx (1 + \Delta L / L)/L\) with \(\Delta L/L = \lambda V_\mathrm{DS}\), so that

This so-called channel-length modulation leads to a reduced output impedance of the MOSFET, i.e., a nonzero output conductance (ideally, \(\lambda = 0\) and thus \(g_\mathrm{ds}= 0\)):

Since \(\lambda \propto 1/L\), the output resistance can be improved by increasing \(L\) beyond the minimum length, which is usually done when using the MOSFET as a current source. By scaling \(W\) along with \(L\), the aspect ratio can be kept constant. Figure 12 shows the output characteristic including channel-length modulation; note the finite slope of the curves in saturation.

Channel-Length Modulation

Figure 12: NMOS output characteristic including channel-length modulation (\(\mu_\mathrm{n} C'_\mathrm{ox} = 280\,\mathrm{\mu A/V^2}\), \(W/L = 10\), \(V_\mathrm{th} = 0.5\,\)V, \(\lambda = 0.1\,\mathrm{V}^{-1}\)).

NMOS output characteristic including channel-length modulation (\(\mu_\mathrm{n} C'_\mathrm{ox} = 280\,\mathrm{\mu A/V^2}\), \(W/L = 10\), \(V_\mathrm{th} = 0.5\,\)V, \(\lambda = 0.1\,\mathrm{V}^{-1}\)). The curves in saturation now exhibit a finite slope, corresponding to a nonzero output conductance.

2.3.3 Velocity Saturation

\[ v_\mathrm{eff} = \begin{cases} \dfrac{\mu_\mathrm{n}E_\mathrm{DS}}{1 + {E_\mathrm{DS}}/{E_\mathrm{sat}}} & \text{if } E_\mathrm{DS} \leq E_\mathrm{sat} = {2 v_\mathrm{sat}}/{\mu_\mathrm{n}} \\[1ex] v_\mathrm{sat} & \text{otherwise} \end{cases} \tag{19}\]

In the derivation of Equation 9, we assumed that the velocity of the carriers in the channel is given by \(v = \mu_\mathrm{n}E_\mathrm{DS}\). This is only true up to a certain speed limit of the carriers in silicon, which is around \(v_\mathrm{sat} = 10^7\,\text{cm/s}\). To take this velocity saturation into account, the following empirical model for the effective velocity can be used in the derivation:

If the MOSFET enters the velocity-saturation regime, the square-law relation no longer holds, and the drain current is given by

Velocity Saturation

\[ I_\mathrm{D}= v_\mathrm{sat} C'_\mathrm{ox}W (V_\mathrm{GS}- V_\mathrm{th}). \tag{20}\]

\[ g_\mathrm{m,sat} = v_\mathrm{sat} C'_\mathrm{ox}W \tag{21}\]

In velocity saturation, \(I_\mathrm{D}\) is not a quadratic but a linear function of the overdrive voltage, and the transconductance hence saturates at

This result means that increasing the drain current beyond the velocity-saturation point does not result in an increased \(g_\mathrm{m}\), which is usually not useful.

In sub-micron technologies, it is relatively easy to reach velocity saturation: with \(\mu_\mathrm{n}= 280\,\text{cm}^2/(\text{V}\cdot\text{s})\), the resulting critical field is \(E_\mathrm{sat} = 7.1\,\text{V}/\mu\text{m}\), which is reached in a 0.13 µm CMOS technology at an overdrive of \(V_\mathrm{od}\approx 0.9\,\text{V}\)—achievable with a supply voltage of \(V_\mathrm{DD}= 1.5\,\text{V}\) and \(V_\mathrm{th}= 0.5\,\text{V}\)! Note that the stated \(\mu_\mathrm{n}\) is considerably lower than the mobility of pure silicon, because doping reduces mobility—yet another trade-off.¹

1. The mobility value used here is not fully consistent with the process constant \(K_\mathrm{n} = \mu_\mathrm{n}C'_\mathrm{ox}= 280\,\mu\text{A/V}^2\) in Table 1, which (with \(C'_\mathrm{ox}= 17.3\,\text{fF/µm}^2\)) would imply an effective \(\mu_\mathrm{n}\approx 160\,\text{cm}^2/(\text{V}\cdot\text{s})\). The effective mobility depends strongly on the vertical field and thus on bias; such spread between simple hand-calculation parameters is normal and is one more reason to verify all sizing choices by simulation.

2.3.4 Mobility Degradation with Vertical Field

\[ \mu_\mathrm{n,eff} = \frac{\mu_\mathrm{n}}{1 + \Theta (V_\mathrm{GS}- V_\mathrm{th})} \tag{22}\]

\[ I_\mathrm{D}= \frac{1}{2} \frac{\mu_\mathrm{n}C'_\mathrm{ox}}{1 + \Theta V_\mathrm{od}} \frac{W}{L} V_\mathrm{od}^2 \approx \frac{1}{2} \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} ( V_\mathrm{od}^2 - \Theta V_\mathrm{od}^3 ) \tag{23}\]

With high \(V_\mathrm{GS}\), the channel is confined to a narrow region at the surface, leading to more carrier scattering and thus lower mobility (remember that at the SiO\(_2\)-silicon interface, scattering is more pronounced). We can model this effect empirically by setting

and using this \(\mu_\mathrm{n,eff}\) instead of \(\mu_\mathrm{n}\) in the saturation current (Equation 13):

This introduces a cubic nonlinearity into an otherwise quadratic relationship, which can be relevant for precision analog and high-frequency circuits, with \(\Theta \approx (10^{-9}\,\text{m/V}) / t_\mathrm{ox}= 0.5\,\text{V}^{-1}\) for \(t_\mathrm{ox}= 2\,\text{nm}\).

2.3.5 Subthreshold Conduction

\[ I_\mathrm{D}= I_0 \frac{W}{L} e^{\frac{V_\mathrm{GS}}{n V_\mathrm{T}}} \left( 1 - e^{-\frac{V_\mathrm{DS}}{V_\mathrm{T}}} \right) = \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} \, 2 n V_\mathrm{T}^2 \, e^{\frac{V_\mathrm{GS}- V_\mathrm{th}}{n V_\mathrm{T}}} \left( 1 - e^{-\frac{V_\mathrm{DS}}{V_\mathrm{T}}} \right). \tag{24}\]

\[ n = 1 + \frac{C'_\mathrm{dep}}{C'_\mathrm{ox}} \tag{25}\]

In the derivation of Equation 7, we assumed that inversion sets in abruptly when the surface potential reaches \(2 \Phi_\mathrm{B}\). However, even before reaching this level, there are already electrons present in the channel (for the NMOS; holes for the PMOS), which lead to conduction between drain and source even for \(V_\mathrm{GS}< V_\mathrm{th}\).

This mode of operation is called subthreshold conduction, and it leads to a leakage current based on diffusion when the MOSFET should be off. The drain current in this regime is described by

The nonideality factor (or slope factor) \(n\) is defined by (see Equation 16)

and is on the order of 1 (perfect MOSFET) to 2 (pretty bad). Using the values of \(C'_\mathrm{ox}\) and \(C'_\mathrm{dep}\) from the previous examples, we get \(n = 1.29\). \(V_\mathrm{T}= k T / q\) is the well-known thermal voltage of \(25.8\,\text{mV}\) at \(300\,\text{K}\), and

Subthreshold Conduction

\[ I_0 = \mu_\mathrm{n}C'_\mathrm{ox}\, 2 n V_\mathrm{T}^2 \, e^{-\frac{V_\mathrm{th}}{n V_\mathrm{T}}}. \]

\[ C'_\mathrm{dep}= \sqrt{\frac{q N_\mathrm{a}\varepsilon_\mathrm{si}}{2 \cdot 2 \Phi_\mathrm{B}}} \]

Note that the depletion capacitance \(C'_\mathrm{dep}\) is given by Equation 3 evaluated at \(\Phi_\mathrm{S}= 2\Phi_\mathrm{B}\):

The inversion condition used in the derivation of the threshold voltage in Equation 7 is the point where the electron concentration at the surface equals the bulk doping concentration \(N_\mathrm{a}\)—but even before this condition is met, there are electrons in the channel. Another way to look at this is that the surface potential effectively forward-biases the channel-source junction (since the channel region is \(p\)-type and the source is \(n^+\)), which can be seen in the plot of \(\Phi_\mathrm{S}\) in Figure 7. When the forward bias of this junction is gradually increased, electrons are injected into the channel area (similar to a BJT), moving across the channel by diffusion, and collected by the drain. At the point where the channel switches from \(p\)- to \(n\)-type due to inversion, this “diode” approaches an ohmic connection linking drain and source.

Although this weak inversion mode of the MOSFET is generally unwanted in digital circuits (as it leads to leakage currents), it is very useful for low-power analog (and digital) operation. Assuming \(V_\mathrm{DS}> 4 V_\mathrm{T}\approx 100\,\text{mV}\), then

Subthreshold Conduction

\[ I_\mathrm{D}\approx I_0 \frac{W}{L} e^{\frac{V_\mathrm{GS}}{n V_\mathrm{T}}} \]

\[ g_\mathrm{m}= \frac{\partial I_\mathrm{D}}{\partial V_\mathrm{GS}} = \frac{I_\mathrm{D}}{n V_\mathrm{T}} \tag{26}\]

and the resulting transconductance is

This transconductance in weak inversion is similar to that of a BJT, except for the reduction by the factor \(n\)!

2.3.6 MOSFET I/V Characteristic Including the Body Effect

\[ \int_{0}^{L} I_\mathrm{D}\, dx = \mu_\mathrm{n}C'_\mathrm{ox}W \int_{0}^{V_\mathrm{DS}} ( V_\mathrm{GS}- n V_\mathrm{cs} - V_\mathrm{th}) \, dV_\mathrm{cs} \]

\[ I_\mathrm{D}= \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} \left[ ( V_\mathrm{GS}- V_\mathrm{th}) V_\mathrm{DS}- \frac{n}{2} V_\mathrm{DS}^2 \right] \tag{27}\]

In the earlier derivation of the square law (Equation 10), we made a deliberate error: when the channel potential \(V_\mathrm{cs}\) departs from \(V_\mathrm{S}\) towards \(V_\mathrm{D}\), we need to take the body effect along the channel into account by using \(n V_\mathrm{cs}\) instead of \(V_\mathrm{cs}\), so \(Q'_\mathrm{inv}(x) = C'_\mathrm{ox}(V_\mathrm{GS}- n V_\mathrm{cs} - V_\mathrm{th})\). The corrected derivation is then

resulting in

In the deep-triode region, there is no difference from the previous result, as the term \(n V_\mathrm{DS}^2 / 2\) vanishes for small \(V_\mathrm{DS}\). The saturation voltage is now \(V_\mathrm{DS,sat} = (V_\mathrm{GS}- V_\mathrm{th}) / n\), and the drain current in saturation becomes (compare to Equation 13)

MOSFET I/V Characteristic Including the Body Effect

\[ I_\mathrm{D}= I_\mathrm{DS,sat} = \frac{1}{2 n} \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} (V_\mathrm{GS}- V_\mathrm{th})^2. \tag{28}\]

\[ g_\mathrm{m}= \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} \frac{V_\mathrm{GS}- V_\mathrm{th}}{n} = \sqrt{\frac{2}{n} \mu_\mathrm{n}C'_\mathrm{ox}\frac{W}{L} I_\mathrm{D}} = \frac{2 I_\mathrm{D}}{V_\mathrm{GS}- V_\mathrm{th}}. \tag{29}\]

The corrected expressions for the transconductance are

2.4 MOSFET AC Operation

MOSFET AC Operation

• The oxide capacitance between the gate and the channel, \(C_\mathrm{gg}= C'_\mathrm{ox}W L\).
• The gate-drain and gate-source overlap capacitances \(C_\mathrm{ov} = C'_\mathrm{ov} W\).
• The junction capacitance between drain/source and substrate, \(C_\mathrm{j} = C_\mathrm{j0} / (1 + V_\mathrm{DB | SB} / \Phi_\mathrm{B})^m\) with \(m \approx 0.3 \ldots 0.4\). \(C_\mathrm{j0}\) is defined by the area and perimeter of the drain/source regions.
• The depletion capacitance between the channel (the inversion layer) and the substrate, \(C_\mathrm{dep} = C'_\mathrm{dep}W L\).

So far, we have only considered the dc operation of the MOSFET, but the physical construction of the transistor leads to unwanted capacitances and resistances, which need to be accounted for in dynamic operation. The most important capacitive elements are:

To identify the dominant capacitive elements between gate-source (\(C_\mathrm{GS}\)) and gate-drain (\(C_\mathrm{GD}\)), we need to distinguish between the triode and the saturation region, see Table 2.

MOSFET AC Operation

Table 2: Dominant gate capacitances of the MOSFET in the triode and saturation regions

Operating region	\(C_\mathrm{GS}\)	\(C_\mathrm{GD}\)
Triode	\(\frac{1}{2} C_\mathrm{gg}+ C_\mathrm{ov}\)	\(\frac{1}{2} C_\mathrm{gg}+ C_\mathrm{ov}\)
Saturation	\(\frac{2}{3} C_\mathrm{gg}+ C_\mathrm{ov}\)	\(C_\mathrm{ov}\)

In addition to these capacitances, the resistance of the gate connection is usually dominant among the parasitic resistances. The end-to-end resistance of the gate stripe is \(R_\square \cdot W / L\) (with the sheet resistance \(R_\square\) set by the gate material). Due to the distributed nature of the gate along the width of the transistor, a reasonable lumped model for a single-sided gate contact is

MOSFET AC Operation

\[ R_\mathrm{G} = \frac{1}{3} R_\square \frac{W}{L} \tag{30}\]

\[ R_\mathrm{G} = \left( \frac{1}{3} R_\square \frac{W}{2 \cdot L} \right) \parallel \left( \frac{1}{3} R_\square \frac{W}{2 \cdot L} \right) = \frac{1}{12} R_\square \frac{W}{L} \tag{31}\]

Using a double-sided gate contact, the effective gate resistance is reduced to

The impact of \(R_\mathrm{G}\) on performance can be further minimized by constructing a large transistor out of \(m\) smaller transistors connected in parallel (“fingers”). If the total width is \(W = m W'\) (with each finger having width \(W'\)), the gates of all unit transistors are connected in parallel, and the effective single-sided gate resistance becomes

MOSFET AC Operation

\[ R_\mathrm{G,eff} = \frac{R'_\mathrm{G}}{m} = \frac{\frac{1}{3} R_\square \frac{W}{m \cdot L}}{m} = \frac{1}{m^2} R_\mathrm{G} \tag{32}\]

A typical analog/RF layout therefore splits a wide transistor into several fingers of limited length (a few µm), uses double-sided gate contacts, and surrounds the device with a closed well-contact ring; the multi-finger layout technique is discussed in detail in Section 4.5.

2.5 MOSFET Small-Signal Model

MOSFET Small-Signal Model

\[ g_\mathrm{mb}= g_\mathrm{m}\frac{\gamma}{2 \sqrt{2 \Phi_\mathrm{B}+ V_\mathrm{SB}}}. \]

The complete small-signal model of a MOSFET in saturation is shown in Figure 13. The transconductance \(g_\mathrm{m}\) is modeled by a voltage-controlled current source, as is the body effect, which contributes a back-gate transconductance

MOSFET Small-Signal Model

Figure 13: Complete small-signal model of the MOSFET in saturation, including the gate resistance, the capacitances to all terminals, the transconductance \(g_\mathrm{m}\), the back-gate transconductance \(g_\mathrm{mb}\), and the output conductance \(g_\mathrm{ds}\).

2.5.1 High-Frequency Operation

\[ I_\mathrm{ds} (j \omega)= I_\mathrm{gs}(j \omega) \frac{g_\mathrm{m}- j \omega C_\mathrm{GD}}{j \omega (C_\mathrm{GS}+ C_\mathrm{GD})} \]

\[ \omega_\mathrm{T} = 2 \pi f_\mathrm{T}\approx \frac{g_\mathrm{m}}{C_\mathrm{GS}+ C_\mathrm{GD}} \approx \frac{g_\mathrm{m}}{C_\mathrm{GG}} \approx \frac{3}{2 n} \frac{\mu}{L^2} (V_\mathrm{GS}- V_\mathrm{th}). \tag{33}\]

For high-frequency operation, the definition of the transit frequency \(f_\mathrm{T}\) is useful; this is the frequency where the magnitude of the current gain \(|I_\mathrm{ds}| / |I_\mathrm{gs}|\) falls to one. The ac drain current can be calculated based on the small-signal model:

The transit frequency is thus (extrapolating the low-frequency transfer function)

In addition, the maximum oscillation frequency \(f_\mathrm{max}\) is a useful metric; it is the frequency where the maximum available power gain drops to one (\(\text{MAG} = 0\,\text{dB}\)):

High-Frequency Operation

\[ f_\mathrm{max} \approx \sqrt{\frac{f_\mathrm{T}}{8 \pi R_\mathrm{G} C_\mathrm{GD}}} \tag{34}\]

2.5.2 Simplified Small-Signal Models

In most cases, a simplified model is sufficient for hand calculations. Neglecting most model elements, the two models shown in Figure 14 can be used in the saturation region. The left π-model is usually better suited for circuits with the signal input at the gate (like in a common-source or common-drain amplifier), whereas the right \(\tau\)-model is advantageous when the input is at the source (like in a common-gate amplifier).

Simplified Small-Signal Models

Figure 14: Simplified small-signal models of the MOSFET in saturation for hand calculations: \(\pi\)-model (left), preferred when the input is at the gate, and \(\tau\)-model (right), preferred when the input is at the source.

Simplified small-signal models of the MOSFET in saturation for hand calculations: \(\pi\)-model (left), preferred when the input is at the gate, and \(\tau\)-model (right), preferred when the input is at the source. In the \(\tau\)-model, the current through the resistor \(1/g_\mathrm{m}\) equals \(i_\mathrm{ds}\), which is mirrored by the controlled source into the drain.

2.6 MOSFET Scaling

MOSFET Scaling

Figure 15: CMOS technology scaling trend: minimum feature size (node name) versus year of first volume production, with key technology innovations annotated (data compiled from public sources, e.g., wikichip.org).

Making MOSFETs smaller has benefits for power, performance, and area (PPA). Traditionally, every 2–3 years a scaled (= smaller) CMOS technology node has been introduced. In Figure 15, the technology nodes are plotted versus their year of first volume production; note the logarithmic axis!

In the beginning, the node name stated the minimum feature size of the given technology, which is usually the minimum gate length (\(L_\mathrm{min}\)): in a 130 nm technology, \(L_\mathrm{min} = 130\,\text{nm}\). This holds well down to about the 90 nm node; from there on the printed gate length is already shorter than the node name (the 65 nm node used a physical gate length of roughly 35 nm), and from the 22/20 nm node onwards the technology name is merely a “label.” Since traditionally a scaling factor of \(\sqrt{2}\) has been used, the node names reflect this: 350 → 250 → 180 → 130 → 90 → 65 → 45 → 32/28 → 22/20 → 16/14 → 10 → 7 → 5 → 3 → 2 → 1.6 nm.

2.6.1 Scaling Theory

1. Reduce all lateral and vertical dimensions by \(\alpha\) (\(\alpha = \sqrt{2}\) for classical scaling; the area of a MOSFET thus shrinks by \(\alpha^2 = 2\)).
2. Reduce the threshold voltage \(V_\mathrm{th}\) and the supply voltage \(V_\mathrm{DD}\) by \(\alpha\).
3. Increase all doping levels by \(\alpha\).

The ideal scaling theory follows three rules, formulated by R. Dennard in 1974 (Dennard et al. 1974), to generate the next CMOS technology node from the current one:

This scaling is called constant-field scaling. If we apply these rules, the MOSFET parameters in the shrunken technology (marked by \(^*\)) scale as follows. The drain saturation current is reduced by \(\alpha\):

Scaling Theory

\[ I^*_\mathrm{D} = \frac{1}{2} \mu_\mathrm{n}(\alpha C'_\mathrm{ox}) \frac{W / \alpha}{L / \alpha} \left( \frac{V_\mathrm{GS}}{\alpha} - \frac{V_\mathrm{th}}{\alpha} \right)^2 = \frac{1}{\alpha} I_\mathrm{D} \]

\[ C^*_\mathrm{gg} = \frac{W}{\alpha} \frac{L}{\alpha} (\alpha C'_\mathrm{ox}) = \frac{1}{\alpha} C_\mathrm{gg} \]

This is offset by the fact that the input capacitance is also reduced:

To estimate the scaling of the gate delay of logic gates built from scaled devices, we use the simple model \(T_\mathrm{d} \propto C_\mathrm{gg}V_\mathrm{DD}/ I_\mathrm{D}\), which relates the gate delay to the time it takes to charge or discharge the load capacitance of a driven gate between the supply rails. The scaled delay is

Scaling Theory

\[ T^*_\mathrm{d} = \frac{C_\mathrm{gg}/ \alpha}{I_\mathrm{D}/ \alpha} \frac{V_\mathrm{DD}}{\alpha} = \frac{1}{\alpha} T_\mathrm{d} \]

\[ P^*_\mathrm{dyn} = f_\mathrm{clk} \frac{C_\mathrm{dyn}}{\alpha} \left( \frac{V_\mathrm{DD}}{\alpha} \right)^2 = \frac{1}{\alpha^3} P_\mathrm{dyn} \]

The speed of digital circuits thus benefits from scaling, as the gate delay shrinks in each new technology node! Using a simple model for the dynamic power consumption of CMOS logic, \(P_\mathrm{dyn} = f_\mathrm{clk} C_\mathrm{dyn} V_\mathrm{DD}^2\) (where \(f_\mathrm{clk}\) is the clock frequency and \(C_\mathrm{dyn} \propto C_\mathrm{gg}\) is the total switched capacitance), we see that

so the dynamic power consumption of a scaled logic circuit benefits dramatically. Note that the power per function, clocked at the same frequency, scales by \(\alpha^{-3}\)—but since we can also increase the clock frequency by \(\alpha\), and can integrate \(\alpha^2\) more gates per area, the total power consumption would stay constant if we fully exploited the scaling benefit. To improve power, performance, and area (PPA) simultaneously, a trade-off has to be found.

2.6.2 Analog Scaling

\[ g^*_\mathrm{m} = \mu_\mathrm{n}(\alpha C'_\mathrm{ox}) \frac{W / \alpha}{L / \alpha} \frac{V_\mathrm{GS}- V_\mathrm{th}}{\alpha} = g_\mathrm{m} \]

\[ f^*_\mathrm{T} = \frac{1}{2 \pi} \frac{g_\mathrm{m}}{C_\mathrm{gg}/ \alpha} = \alpha f_\mathrm{T} \]

While there is a clear scaling benefit for digital circuits, the benefits for analog circuits are less clear. Generally, the reduction of \(V_\mathrm{DD}\) is a drawback, since it likely reduces the dynamic range when processing voltage signals. The transconductance scales like

so it seems to be scale-invariant. However, there is a benefit in device speed, as the transit frequency scales like

so the speed of the MOSFET increases, opening the door to better analog and RF performance, albeit at lower supply voltages.

2.6.3 Scaling Summary

Table 3: Constant-field (Dennard) scaling of MOSFET parameters

Parameter	Symbol	Scaling factor
Gate length	\(L_\mathrm{min}\)	\(\alpha^{-1}\)
MOSFET area	\(W L\)	\(\alpha^{-2}\)
Gate oxide thickness	\(t_\mathrm{ox}\)	\(\alpha^{-1}\)
Substrate doping	\(N_\mathrm{a}\)	\(\alpha\)
Drain current in saturation	\(I_\mathrm{D}\)	\(\alpha^{-1}\)
Gate capacitance	\(C_\mathrm{GS}\)	\(\alpha^{-1}\)
Supply voltage	\(V_\mathrm{DD}\)	\(\alpha^{-1}\)
Threshold voltage	\(V_\mathrm{th}\)	\(\alpha^{-1}\)
Gate delay	\(T_\mathrm{d}\)	\(\alpha^{-1}\)
Clock frequency	\(f_\mathrm{clk}\)	\(\alpha\)
Dynamic power consumption per gate	\(P_\mathrm{dyn}\)	\(\alpha^{-3}\)

Table 3 summarizes the constant-field scaling factors derived above. Scaling equations fitted to real technology data from 180 nm down to 7 nm can be found in (Stillmaker and Baas 2017).

2.6.4 Interconnect Scaling

\[ \frac{R^*}{l} = \rho \frac{1}{(t / \alpha) (w / \alpha)} = \alpha^2 \frac{R}{l} \]

\[ \frac{C^*_\mathrm{f}}{l} = \varepsilon_\mathrm{ox}\frac{t / \alpha}{s / \alpha} = \frac{C_\mathrm{f}}{l} \]

As the MOSFETs get smaller, the metal wiring also needs to scale to finer dimensions. We assume that, along with the lateral dimensions, the metal thickness and the dielectric inter-metal insulation scale down as well. The resistance per length of a scaled metal wire (with thickness \(t\) and width \(w\)) scales as

so the wires get significantly more resistive! The wire-to-wire fringe capacitance per length for a minimum-width wire with minimum spacing \(s\) scales as

and the vertical coupling capacitance per length (with insulator thickness \(h\)) scales as

Interconnect Scaling

\[ \frac{C^*_\mathrm{p}}{l} = \varepsilon_\mathrm{ox}\frac{w / \alpha}{h / \alpha} = \frac{C_\mathrm{p}}{l} \]

\[ \frac{T^*_\mathrm{wire}}{l^2} \propto \frac{R^*}{l} \left( \frac{C^*_\mathrm{f}}{l} + \frac{C^*_\mathrm{p}}{l} \right) = \alpha^2 \frac{T_\mathrm{wire}}{l^2} \]

so both capacitance values are, to first order, invariant to scaling. The RC wire delay per squared length is thus

For short routes, this increased relative delay is offset by the length scaling, so that

Interconnect Scaling

\[ T^*_\mathrm{wire} \propto \left( \frac{l}{\alpha} \right)^2 \frac{T^*_\mathrm{wire}}{l^2} = T_\mathrm{wire} \]

For long routes, however, the wire delay increases significantly. To cope with this delay, other solutions are needed: using multiple wiring levels (lower metals levels scaled for density, higher ones un-scaled for speed), or adapting the architecture, e.g., pipelining long-range data transfers.

2.7 MOSFET Short-Channel Effects

2.7.1 Subthreshold Leakage

\[ I_\mathrm{D}= 100\,\text{nA} \cdot \frac{W}{L} \, e^{\frac{V_\mathrm{GS}- V_\mathrm{th}}{n V_\mathrm{T}}} \tag{35}\]

\[ n = 1 + \frac{C'_\mathrm{dep}}{C'_\mathrm{ox}} = 1 + \underbrace{\frac{\varepsilon_\mathrm{si}}{\varepsilon_\mathrm{ox}}}_{\approx 3} \frac{t_\mathrm{ox}}{W_\mathrm{dep}} \tag{36}\]

As the MOSFET gate length is scaled below \(1\,\mu\text{m}\), various imperfections kick in. We discuss subthreshold conduction and leakage, gate oxide leakage, and drain-induced barrier lowering (DIBL). Other effects, like random dopant fluctuation (RDF), poly depletion, or quantum-mechanical effects, are not covered here.

Revisiting Equation 24 and neglecting the \(V_\mathrm{DS}\)-dependent term, we can re-formulate the subthreshold drain current as

Here, \(V_\mathrm{th}\) has been re-defined as the \(V_\mathrm{GS}\) at which \(I_\mathrm{D}= 100\,\text{nA} \cdot W / L\), which is a quite practical definition for leakage current discussions. The nonideality factor can also be written as

Using Equation 35, we see that the leakage current in the off-state (\(V_\mathrm{GS}= 0\)) is impacted by only two parameters (\(W/L\) is usually fixed by the circuit design):

Subthreshold Leakage

\[ I_\mathrm{leak} = 100\,\text{nA} \cdot \frac{W}{L} \, e^{-\frac{V_\mathrm{th}}{n V_\mathrm{T}}} \tag{37}\]

Subthreshold Leakage

1. The threshold voltage \(V_\mathrm{th}\): a lower \(V_\mathrm{th}\) increases the overdrive when the MOSFET is turned on and thus reduces the gate delay, but it exponentially increases the leakage current.
2. The nonideality factor \(n\) (ideally, \(n = 1\)).

2.7.2 Subthreshold Slope

\[ S = \left[ \frac{\partial (\log_{10} I_\mathrm{D})}{\partial V_\mathrm{GS}} \right]^{-1} = \frac{n V_\mathrm{T}}{\log_{10}(e)} = 2.3 \, n V_\mathrm{T} \tag{38}\]

To quantify the “turn-off” behavior of a MOSFET, the subthreshold slope \(S\) is defined, starting from Equation 35, and consisting of the two only parameters \(V_\mathrm{T}\) and \(n\):

The subthreshold slope expresses which change of \(V_\mathrm{GS}\) lowers (or increases) the drain current by a factor of ten. Ideally, \(S\) should be as small as possible, meaning that the MOSFET can be turned off rapidly with a small change of \(V_\mathrm{GS}\):

Subthreshold Slope

• The lower bound is \(S = 2.3 V_\mathrm{T}= 59.4\,\text{mV/dec}\) at \(300\,\text{K}\).
• Using \(n = 1.29\) from the previous example, \(S = 76.6\,\text{mV/dec}\), which is a good value; \(S\) for bulk CMOS is in the range of 80 to 120 mV/dec.

The impact of the subthreshold slope essentially stopped the scaling of \(V_\mathrm{DD}\) and \(V_\mathrm{th}\), as the leakage current would otherwise become impractically large. This issue is exacerbated by the temperature dependence of the threshold voltage of \(\approx -1\,\text{mV/K}\) and its process variation on the order of \(\pm 50\,\text{mV}\). A threshold-voltage shift of a hundred millivolts may not sound like much, but it enters the leakage exponentially and thus has a drastic impact! Figure 16 shows how the supply voltage stopped scaling at around 0.8 V.

Subthreshold Slope

Figure 16: Nominal core supply voltage versus CMOS technology node.

Nominal core supply voltage versus CMOS technology node. Below roughly 90 nm, the supply voltage no longer scales with the feature size but flattens out around 1 V, limited by the subthreshold leakage (data after Stillmaker and Baas, 2017).

2.7.3 Gate Oxide Leakage

• The breakdown voltage of the oxide is reduced, mandating a low \(V_\mathrm{DD}\).
• The gate leakage current increases dramatically due to quantum-mechanical tunneling.

As can be seen in Equation 36, to minimize \(n\) (and thus the subthreshold slope), and also to increase the drain current in saturation, \(C'_\mathrm{ox}\) needs to be maximized. This has driven the scaling down of the gate oxide thickness, as discussed in the scaling rules. Over the years, the oxide thickness has been reduced from 300 nm to 1.2 nm, but severe issues appear once the oxide is only a few nanometers thick:

An alternative is needed to increase \(C'_\mathrm{ox}\) without further reducing \(t_\mathrm{ox}\): the introduction of alternative gate dielectrics with increased permittivity, the so-called high-k gate dielectrics. One suitable material is hafnium dioxide: while SiO₂ has \(\varepsilon_\mathrm{r} = 3.9\), HfO₂ offers \(\varepsilon_\mathrm{r} = 24\). However, there are potential manufacturing issues, like chemical reactions with the silicon substrate and the gate material, reliability concerns, and reduced surface mobility. Still, high-k dielectrics are now widely used in modern CMOS processes.

2.7.4 Drain-Induced Barrier Lowering (DIBL)

\[ \Delta V_\mathrm{th}= - (V_\mathrm{DS}+ 0.4\,\text{V}) \, e^{-L/l_\mathrm{d}} \tag{39}\]

In scaled MOSFETs, there exists another parasitic effect that lowers \(V_\mathrm{th}\) as a function of \(L\), called drain-induced barrier lowering (DIBL). (Remember that lowering \(V_\mathrm{th}\) has an exponential effect on the leakage current!) This lowering of \(V_\mathrm{th}\) with decreasing \(L\) is also called the short-channel effect (SCE). Note that there is also a reverse short-channel effect (RSCE), which increases \(V_\mathrm{th}\) with decreasing \(L\), caused by halo implants around drain and source in modern CMOS processes. Effectively, \(V_\mathrm{th}= f(L)\) can be a wild function of the MOSFET length, so devices will only match if constructed with the same \(L\)! Note that \(V_\mathrm{th}\) also depends on \(V_\mathrm{DS}\) due to DIBL, and on device \(W\), as well as temperature, and other second-order effects, so ultimately \(V_\mathrm{th}= f(L, W, V_\mathrm{DS}, T)\)!

The impact of \(L\) and \(V_\mathrm{DS}\) on \(V_\mathrm{th}\) can be modeled by

and is illustrated in Figure 17. The DIBL characteristic length is \(l_\mathrm{d} \propto \sqrt[3]{t_\mathrm{ox}W_\mathrm{dep}X_\mathrm{j}}\). To reduce \(l_\mathrm{d}\), one or all of these parameters must be reduced:

Drain-Induced Barrier Lowering (DIBL)

• The oxide thickness \(t_\mathrm{ox}\), which has already been discussed in the context of gate leakage.
• The depletion width \(W_\mathrm{dep}\).
• The drain junction depth \(X_\mathrm{j}\).

Drain-Induced Barrier Lowering (DIBL)

Figure 17: Threshold-voltage shift \(\Delta V_\mathrm{th}\) due to DIBL as a function of gate length, calculated with the model of Equation 39 for a characteristic length \(l_\mathrm{d} = 15\,\)nm.

Threshold-voltage shift \(\Delta V_\mathrm{th}\) due to DIBL as a function of gate length, calculated with the model of Equation 39 for a characteristic length \(l_\mathrm{d} = 15\,\)nm. For short gate lengths and high drain voltages, the threshold voltage drops rapidly (compare, e.g., the measured data for a 65 nm technology in (Goto et al. 2003)).

2.7.5 Solving DIBL: The Ultra-Thin-Body MOSFET

• Since much less body doping \(N_\mathrm{a}\) is needed, the carrier mobility is higher.
• There is no (or only a small) body effect, since the body is floating and fully depleted.
• The drain/source-to-bulk capacitance is largely reduced and almost constant.

Reducing the depletion width and the junction depth requires increasing \(N_\mathrm{a}\) (see Equation 2). However, increasing \(N_\mathrm{a}\) also increases \(V_\mathrm{th}\) (see Equation 7), which must be counteracted by increasing \(C'_\mathrm{ox}\)—but there are limits due to gate leakage and breakdown, as discussed before. In addition, increasing \(N_\mathrm{a}\) increases the subthreshold slope (see Equation 36) and lowers the mobility due to dopant scattering. So an alternative to ever-increasing substrate doping had to be found.

As scaling up \(N_\mathrm{a}\) to constrain the vertical dimensions has reached its limits, an alternative solution is to remove the silicon under the channel to physically constrain \(W_\mathrm{dep}\) and \(X_\mathrm{j}\). In the ultra-thin-body (UTB) MOSFET, the silicon channel is realized on top of a layer of SiO₂, so the depletion and junction depths are limited to the silicon film thickness \(t_\mathrm{si} \leq L/4\). This is called silicon-on-insulator (SOI) technology; the structure is shown in Figure 18 (a). Additional advantages are:

The disadvantage is the higher cost of the SOI wafers, as manufacturing the Si-SiO₂-Si stack is expensive.

2.7.6 Solving DIBL: FinFET and Nanosheet

• The device width is quantized, with \(W = W_\mathrm{F} + 2 H_\mathrm{F}\) per fin (\(W_\mathrm{F}\) is the width and \(H_\mathrm{F}\) the height of the fin), so the circuit design style must be adapted (the design parameter is the number of fins \(N_\mathrm{F}\) instead of \(W\)).
• Drain and source are contacted at the ends of the fin, so the series resistances \(R_\mathrm{S}\) and \(R_\mathrm{D}\) are higher, degrading the transconductance due to series feedback: \(g_\mathrm{m,eff} = g_\mathrm{m}/ (1 + g_\mathrm{m}R_\mathrm{S})\).
• Since the subthreshold slope is improved (smaller), the leakage current is lower, which allows lowering \(V_\mathrm{th}\) and \(V_\mathrm{DD}\).

Another alternative is to tilt the silicon channel by 90°, so that it sticks out of the wafer like a “fin,” and to wrap the gate around this fin on three sides: the FinFET (or tri-gate MOSFET), shown in Figure 18 (b). FinFETs have a few important differences compared to bulk MOSFETs:

Solving DIBL: FinFET and Nanosheet

• DIBL and thus \(g_\mathrm{ds}\) are lower, so the MOSFET self-gain \(g_\mathrm{m}/ g_\mathrm{ds}\) is high.
• There is practically no body effect, and due to the low channel doping the mobility is high, leading to improved \(g_\mathrm{m}/I_\mathrm{D}\) and \(\mu_\mathrm{n}\approx \mu_\mathrm{p}\).
• The silicon fins are isolated and surrounded by SiO₂, so self-heating of the fin can be an issue.
• The 3D structure increases the coupling capacitance \(C_\mathrm{ov}\).

Solving DIBL: FinFET and Nanosheet

• A drawback is that SRAM and digital standard cells often use minimum-size transistors, and for yield reasons a minimum-sized FinFET requires two fins—a strong constraint when, e.g., the PMOS needs to be sized differently from the NMOS (the next step up is three fins, a large quantization step).

Solving DIBL: FinFET and Nanosheet

Figure 18: Advanced MOSFET structures with improved electrostatic gate control: (a) ultra-thin-body (UTB) SOI MOSFET shown along the channel, (b) FinFET shown perpendicular to the channel (the gate wraps around the fin on three sides), and (c) nanosheet (gate-all-around) MOSFET, where stacked channels are completely surrounded by the gate.

2.8 Simulated Characteristics in IHP SG13

The evolution of the FinFET is the nanosheet MOSFET, first introduced at the 3 nm node (and used by all foundries at 2 nm) and shown in Figure 18 (c). One advantage is the even better electrostatic control of the gate over the channel, as the stacked channels are completely wrapped by the gate—hence also called gate-all-around (GAA) MOSFET. In addition, the stacked channels can be either \(n\)- or \(p\)-type (or mixed), and could even use different materials, like SiGe or GaAs, opening the door to 3D integration.

Simulated Characteristics in IHP SG13

Figure 19: Simulated output characteristic of an NMOS in IHP SG13 (\(W = 1.3\,\mathrm{\mu m}\), \(L = 0.13\,\mathrm{\mu m}\), \(V_\mathrm{SB} = 0\)) for different gate-source voltages.

To connect the simple models we derived earlier to reality, Figure 19 to Figure 22 show simulated I/V characteristics of NMOS and PMOS devices (\(W = 1.3\,\mu\text{m}\), \(L = 0.13\,\mu\text{m}\), \(V_\mathrm{SB}= 0\)) in the IHP SG13 130 nm CMOS technology, using the foundry’s PSP models. The output characteristics show the triode and saturation regions including channel-length modulation, while the logarithmic transfer characteristics clearly show the exponential subthreshold region and the drain-current dependence on \(V_\mathrm{DS}\) caused by DIBL.

Simulated Characteristics in IHP SG13

Figure 20: Simulated transfer characteristic of an NMOS in IHP SG13 (\(W = 1.3\,\mathrm{\mu m}\), \(L = 0.13\,\mathrm{\mu m}\), \(V_\mathrm{SB} = 0\)) on a logarithmic current axis.

Simulated transfer characteristic of an NMOS in IHP SG13 (\(W = 1.3\,\mathrm{\mu m}\), \(L = 0.13\,\mathrm{\mu m}\), \(V_\mathrm{SB} = 0\)) on a logarithmic current axis. The exponential subthreshold region is clearly visible, as is the drain-voltage dependence caused by DIBL.

Simulated Characteristics in IHP SG13

Figure 21: Simulated output characteristic of a PMOS in IHP SG13 (\(W = 1.3\,\mathrm{\mu m}\), \(L = 0.13\,\mathrm{\mu m}\), \(V_\mathrm{SB} = 0\)) for different gate-source voltages.

Simulated output characteristic of a PMOS in IHP SG13 (\(W = 1.3\,\mathrm{\mu m}\), \(L = 0.13\,\mathrm{\mu m}\), \(V_\mathrm{SB} = 0\)) for different gate-source voltages. Note the lower current level compared to the NMOS due to the lower hole mobility.

Simulated Characteristics in IHP SG13

Figure 22: Simulated transfer characteristic of a PMOS in IHP SG13 (\(W = 1.3\,\mathrm{\mu m}\), \(L = 0.13\,\mathrm{\mu m}\), \(V_\mathrm{SB} = 0\)) on a logarithmic current axis.

2.9 MOSFET Sizing

2.9.1 The \(g_\mathrm{m}/I_\mathrm{D}\) Method

When designing a circuit with MOSFETs, how should one select the parameters like \(I_\mathrm{D}\), \(V_\mathrm{GS}\), \(W\), and \(L\)? For digital designs, this is relatively straightforward: \(L\) is (usually) set to the minimum length, \(W\) is sized according to the driving requirements of the logic circuit, \(V_\mathrm{GS}\) swings between \(V_\mathrm{SS}\) and \(V_\mathrm{DD}\), and no static drain current flows. For analog, mixed-signal, and RF designs, the sizing question is more involved.

In the Analog Circuit Design course, the \(g_\mathrm{m}/I_\mathrm{D}\) method is used to find the proper sizing of a MOSFET depending on the circuit requirements. This method is the “go-to” method, as it uses numerical data found by evaluating the PDK models in a circuit simulator, and it describes the MOSFET correctly in all operating regions.

2.9.2 The Inversion-Coefficient Method

\[ I_\mathrm{S} = \mu C'_\mathrm{ox}\frac{W}{L} \cdot 2 n V_\mathrm{T}^2. \tag{40}\]

\[ \mathrm{IC}= \frac{I_\mathrm{D}}{I_\mathrm{S}} = \left[ \ln \left( 1 + e^{\frac{V_\mathrm{GS}- V_\mathrm{th}}{2 n V_\mathrm{T}}} \right) \right]^2 \tag{41}\]

Despite the practical advantages of the \(g_\mathrm{m}/I_\mathrm{D}\) method, alternative approaches exist, and they can be helpful by providing relatively simple and unified analytical equations which are valid in all MOSFET operating regions. One such method is based on the inversion coefficient, which has been popularized as a design methodology by W. Sansen (Sansen 2015; Sansen 2006). Let us define a specific current

Then, the inversion coefficient \(\mathrm{IC}\) is defined as

The beauty of this approach is that these equations work all the way from weak inversion (subthreshold operation, \(\mathrm{IC}< 0.1\)) through moderate inversion (\(\mathrm{IC}\approx 1\)) to strong inversion (\(\mathrm{IC}> 10\)). Based on the selected \(\mathrm{IC}\), the important device properties can be calculated. The drain current is

The Inversion-Coefficient Method

\[ I_\mathrm{D}= I_\mathrm{S} \cdot \mathrm{IC} \tag{42}\]

\[ g_\mathrm{m}= \frac{I_\mathrm{D}}{n V_\mathrm{T}} \frac{1 - e^{-\sqrt{\mathrm{IC}}}}{\sqrt{\mathrm{IC}}} \tag{43}\]

the transconductance is given by

and the speed of the MOSFET is

The Inversion-Coefficient Method

\[ f_\mathrm{T}= \frac{1}{2 \pi} \frac{3}{2} \frac{\mu}{L^2} V_\mathrm{T}\left( \sqrt{1 + 4 \, \mathrm{IC}} -1 \right) \tag{44}\]

Let us check the asymptotic behavior of these equations against the earlier results (see Table 4).

The Inversion-Coefficient Method

Table 4: Asymptotic behavior of the inversion-coefficient equations in weak and strong inversion

Equation	\(V_\mathrm{GS}\ll V_\mathrm{th}\) (weak inversion)	\(V_\mathrm{GS}\gg V_\mathrm{th}\) (strong inversion)
Equation 41	\(\mathrm{IC}= e^{\frac{V_\mathrm{GS}- V_\mathrm{th}}{n V_\mathrm{T}}}\)	\(\mathrm{IC}= \left( \frac{V_\mathrm{GS}- V_\mathrm{th}}{2 n V_\mathrm{T}} \right)^2\)
Equation 42	\(I_\mathrm{D}= \mu C'_\mathrm{ox}\frac{W}{L} 2 n V_\mathrm{T}^2 e^{\frac{V_\mathrm{GS}- V_\mathrm{th}}{n V_\mathrm{T}}}\)	\(I_\mathrm{D}= \frac{1}{2 n} \mu C'_\mathrm{ox}\frac{W}{L} \left( V_\mathrm{GS}- V_\mathrm{th}\right)^2\)
Equation 43	\(g_\mathrm{m}= \frac{I_\mathrm{D}}{n V_\mathrm{T}}\)	\(g_\mathrm{m}= \frac{2 I_\mathrm{D}}{V_\mathrm{GS}- V_\mathrm{th}}\)
Equation 44	\(f_\mathrm{T}= \frac{1}{2 \pi} \frac{3}{2} \frac{\mu}{L^2} 2 V_\mathrm{T}e^{\frac{V_\mathrm{GS}- V_\mathrm{th}}{n V_\mathrm{T}}}\)	\(f_\mathrm{T}= \frac{1}{2 \pi} \frac{3}{2 n} \frac{\mu}{L^2} \left( V_\mathrm{GS}- V_\mathrm{th}\right)\)

The asymptotes match the subthreshold model (Equation 24) and the corrected square-law model (Equation 28), respectively.

Plotting Equation 43 and Equation 44 versus \(\mathrm{IC}\), as done in Figure 23, reveals the classical trade-off between \(g_\mathrm{m}\)-efficiency (\(g_\mathrm{m}/I_\mathrm{D}\)) and speed (\(f_\mathrm{T}\)). Note that velocity saturation is not represented in this simple model, so \(f_\mathrm{T}\) does not saturate at high \(\mathrm{IC}\) in the plot.

The Inversion-Coefficient Method

Figure 23: Transconductance efficiency \(g_\mathrm{m}/I_\mathrm{D}\) (blue, left axis) and transit frequency \(f_\mathrm{T}\) (red, right axis) versus the inversion coefficient IC, calculated with the analytical model (\(n = 1.3\), \(L = 0.13\,\mathrm{\mu m}\), \(\mu = 280\,\mathrm{cm^2/(V\,s)}\)).

Transconductance efficiency \(g_\mathrm{m}/I_\mathrm{D}\) (blue, left axis) and transit frequency \(f_\mathrm{T}\) (red, right axis) versus the inversion coefficient IC, calculated with the analytical model (\(n = 1.3\), \(L = 0.13\,\mathrm{\mu m}\), \(\mu = 280\,\mathrm{cm^2/(V\,s)}\)). Weak inversion offers the best efficiency, strong inversion the highest speed.

The Inversion-Coefficient Method

Figure 24: Transconductance efficiency \(g_\mathrm{m}/I_\mathrm{D}\) (blue, left axis) and transit frequency \(f_\mathrm{T} = g_\mathrm{m}/(2 \pi C_\mathrm{gg})\) (red, right axis) versus inversion coefficient, extracted from a simulation of an NMOS (\(W/L = 1.3\,\mathrm{\mu m}/0.13\,\mathrm{\mu m}\)) in IHP SG13, using a specific current of \(I_\mathrm{S} = 6\,\mathrm{\mu A}\) extracted from the simulation data.

Figure 24 shows the same trade-off extracted from simulation data of an NMOS (\(W/L = 1.3\,\mu\text{m}/0.13\,\mu\text{m}\)) in IHP SG13. The simulation matches the analytical model well for \(g_\mathrm{m}/I_\mathrm{D}\); the simulated \(f_\mathrm{T}\) comes out higher than the simple model predicts, since the model pessimistically assumes the full \(\frac{2}{3} C'_\mathrm{ox}W L\) gate capacitance at all bias points, while at high \(\mathrm{IC}\) velocity saturation causes the simulated \(f_\mathrm{T}\) to flatten.

Transconductance efficiency \(g_\mathrm{m}/I_\mathrm{D}\) (blue, left axis) and transit frequency \(f_\mathrm{T} = g_\mathrm{m}/(2 \pi C_\mathrm{gg})\) (red, right axis) versus inversion coefficient, extracted from a simulation of an NMOS (\(W/L = 1.3\,\mathrm{\mu m}/0.13\,\mathrm{\mu m}\)) in IHP SG13, using a specific current of \(I_\mathrm{S} = 6\,\mathrm{\mu A}\) extracted from the simulation data. The thin dashed lines show the analytical model (Equation 43 and Equation 44) with \(n = 1.3\), \(L = 0.13\,\mathrm{\mu m}\), and \(\mu = 280\,\mathrm{cm^2/(V\,s)}\).

2.9.3 Sizing Procedure

1. Depending on the trade-off between low power (high \(g_\mathrm{m}/I_\mathrm{D}\)) and high speed (high \(f_\mathrm{T}\)), select the \(\mathrm{IC}\) (often, \(\mathrm{IC}\approx 1\) is a reasonable compromise).
2. Choose either the bias current or the required \(g_\mathrm{m}\), and calculate the other one using Equation 43.
3. Using Equation 42, calculate \(I_\mathrm{S}\) from the known \(I_\mathrm{D}\).
4. Depending on the requirements for transistor speed (minimum \(L\)), matching (large \(W \cdot L\)), or small \(g_\mathrm{ds}\) (large \(L\)), choose the appropriate \(L\); use Equation 40 to calculate the corresponding \(W\).

The design procedure using the inversion coefficient is as follows:

Sizing Procedure

5. Finally, estimate \(f_\mathrm{T}\) using Equation 44. From \(f_\mathrm{T}\), the required bandwidth of the circuit can be estimated, and the sizing can be iterated if necessary.

Now the most important transistor parameters (\(W\), \(L\), \(I_\mathrm{D}\), \(g_\mathrm{m}\), \(V_\mathrm{GS}\), and \(f_\mathrm{T}\)) are selected and known.

2.10 Summary

Summary

• Switch (for small \(V_\mathrm{DS}\) and large \(V_\mathrm{GS}\)).
• Voltage-controlled resistor (since \(g_\mathrm{ds}= f(V_\mathrm{GS})\) in the triode region).
• Voltage-controlled current source (since \(I_\mathrm{D}= f(V_\mathrm{GS})\) in the saturation region).
• Diode (since the MOSFET is off for \(V_\mathrm{GS}< V_\mathrm{th}\) and on otherwise).
• Variable capacitor (using the gate oxide or drain/source junction capacitance).

The MOSFET is a very versatile device, which can, depending on the bias conditions, work as a:

This versatility is nicely illustrated by the collection of two-transistor circuits in (Pretl and Eberlein 2021); the paper, plus posters showing all fifty circuits, is available at the Fifty Nifty Variations of Two-Transistor Circuits homepage.

When making the MOSFET physically small by scaling \(L \ll 1\,\mu\text{m}\) to improve power, performance, and area, various imperfections kick in (like DIBL), causing increased leakage currents and degraded output conductance—so alternative device constructions like SOI, FinFET, and nanosheet MOSFETs have been introduced.

2.11 Appendix: Silicon Material Properties

Appendix: Silicon Material Properties

Table 5: Physical material properties of silicon

Physical parameter of Si	Symbol	Typical value
Lattice constant		0.54 nm
Density		\(5.0 \times 10^{22}\,\text{cm}^{-3}\)
Relative permittivity of Si	\(\varepsilon_\mathrm{r,si}\)	11.9
Relative permittivity of SiO2	\(\varepsilon_\mathrm{r,ox}\)	3.9
Band gap at 300 K	\(E_\mathrm{bg}\)	1.12 eV
Intrinsic carrier concentration at 300 K	\(n_\mathrm{i} = p_\mathrm{i}\)	\(1.0 \times 10^{10}\,\text{cm}^{-3}\)
Linear coefficient of thermal expansion	CTE	\(2.6 \times 10^{-6}\,\text{K}^{-1}\)
Melting point		1415 °C
Mobility of electrons at 300 K	\(\mu_\mathrm{n}\)	1500 cm²/(V s)
Mobility of holes at 300 K	\(\mu_\mathrm{p}\)	450 cm²/(V s)
Thermal conductivity		1.5 W/(cm K)
Breakdown field	\(E_\mathrm{crit}\)	\(3 \times 10^{5}\,\text{V/cm}\)

Table 5 collects the physical properties of silicon used throughout this text.

References

Dennard, Robert H., Fritz H. Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest Bassous, and Andre R. LeBlanc. 1974. “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions.” IEEE Journal of Solid-State Circuits 9 (5): 256–68.

Goto, Ken-ichi et al. 2003. “High Performance 25 nm Gate CMOSFETs for 65 nm Node High Speed MPUs.” IEEE International Electron Devices Meeting (IEDM).

Hu, Chenming. 2010. Modern Semiconductor Devices for Integrated Circuits. Pearson.

Pretl, Harald, and Matthias Eberlein. 2021. “Fifty Nifty Variations of Two-Transistor Circuits: A Tribute to the Versatility of MOSFETs.” IEEE Solid-State Circuits Magazine 13 (3): 38–46. https://doi.org/10.1109/MSSC.2021.3088968.

Razavi, Behzad. 2014. Fundamentals of Microelectronics. 2nd ed. Wiley.

Sansen, Willy. 2015. “Minimum Power in Analog Amplifying Blocks: Presenting a Design Procedure.” IEEE Solid-State Circuits Magazine 7 (4): 83–89. https://doi.org/10.1109/MSSC.2015.2474237.

Sansen, Willy M. C. 2006. Analog Design Essentials. Springer.

Stillmaker, Aaron, and Bevan Baas. 2017. “Scaling Equations for the Accurate Prediction of CMOS Device Performance from 180 nm to 7 nm.” Integration, the VLSI Journal 58: 74–81. https://doi.org/10.1016/j.vlsi.2017.02.002.

Tsividis, Yannis, and Colin McAndrew. 2011. Operation and Modeling of the MOS Transistor. 3rd ed. Oxford University Press.

References